Quadrature signal generation in radio-frequency apparatus and associated methods

ABSTRACT

A radio-frequency (RF) apparatus, which may reside in a receiver or transceiver, includes receive-path circuitry. The receive-path circuitry includes a poly-phase filter and a harmonic filter. The poly-phase filter accepts an input signal and generates two output signals. One output signal of the poly-phase filter constitutes an in-phase (I) signal. The other output signal of the poly-phase filter constitutes a quadrature (Q) signal. The a harmonic filter couples to the poly-phase filter. The harmonic filter accepts as input signals the in-phase and quadrature output signals of the poly-phase filter.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This patent application is a continuation-in-part of, and claimspriority to, U.S. patent application Ser. No. 09/821,340, AttorneyDocket No. SILA:073, titled “Digital Interface in Radio-FrequencyApparatus and Associated Methods,” filed on Mar. 29, 2001. This patentapplication further claims priority to Provisional U.S. PatentApplication Serial No. 60/261,506, Attorney Docket No. SILA:072PZ1,filed on Jan. 12, 2001; and Provisional U.S. Patent Application SerialNo. 60/273,119, Attorney Docket No. SILA:072PZ2, titled “Partitioned RFApparatus with Digital Interface and Associated Methods,” filed on Mar.2, 2001. This patent application also claims priority to, andincorporates by reference, Provisional U.S. Patent Application SerialNo. 60/349,884, Attorney Docket No. SILA:111PZ1, titled “ImprovedQuadrature Generation in Radio Frequency Circuitry,” filed on Jan. 17,2002.

TECHNICAL FIELD OF THE INVENTION

[0002] This invention relates to radio-frequency (RF) receivers andtransceivers. More particularly, the invention concerns improvedquadrature signal generation in RF apparatus, such as receivers andtransceivers.

BACKGROUND

[0003] The proliferation and popularity of mobile radio and telephonyapplications has led to market demand for communication systems with lowcost, low power, and small form-factor radio-frequency (RF)transceivers. As a result, recent research has focused on providingmonolithic transceivers using low-cost complementary metal-oxidesemiconductor (CMOS) technology. Current research has focused onproviding an RF transceiver within a single integrated circuit (IC). Fordiscussions of the research efforts and the issues surrounding theintegration of RF transceivers, see Jacques C. Rudell et al., RecentDevelopments in High Integration Multi-Standard CMOS Transceivers forPersonal Communication Systems, INVITED PAPER AT THE 1998 INTERNATIONALSYMPOSIUM ON LOW POWER ELECTRONICS, MONTEREY, CALIFORNIA; Asad A. Abidi,CMOS Wireless Transceivers: The New Wave, IEEE COMMUNICATIONS MAG.,August 1999, at 119; Jan Crols & Michael S. J. Steyaert, 45 IEEETRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNALPROCESSING 269 (1998); and Jacques C. Rudell et al., A 1.9-GHz Wide-BandIF Double Conversion CMOS Receiver for Cordless Telephone Applications,32 IEEE J. OF SOLID-STATE CIRCUITS 2071 (1997).

[0004] The integration of transceiver circuits is not a trivial problem,as it must take into account the requirements of the transceiver'scircuitry and the communication standards governing the transceiver'soperation. From the perspective of the transceiver's circuitry, RFtransceivers typically include sensitive components susceptible to noiseand interference with one another and with external sources. Integratingthe transceiver's circuitry into one integrated circuit would exacerbateinterference among the various blocks of the transceiver's circuitry.Moreover, communication standards governing RF transceiver operationoutline a set of requirements for noise, inter-modulation, blockingperformance, output power, and spectral emission of the transceiver.Unfortunately, no method for addressing all of the above issues inhigh-performance RF receivers or transceivers, for example, RFtransceivers used in cellular and telephony applications, has beendeveloped. A need therefore exists for techniques of partitioning andintegrating RF receivers or transceivers that would provide low-cost,low form-factor RF transceivers for high-performance applications, forexample, in cellular handsets.

SUMMARY OF THE INVENTION

[0005] This invention contemplates improved quadrature signal generationin signal-processing circuitry, such as RF receivers and transceivers.One aspect of the invention relates to apparatus for generatingquadrature signals. In one embodiment according to the invention, an RFapparatus includes receive-path circuitry. The receive-path circuitryincludes a poly-phase filter and a harmonic filter. The poly-phasefilter accepts an input signal (such as a local oscillator signal or abuffered local oscillator signal) and provides an in-phase signal and aquadrature signal. The harmonic filter couples to the poly-phase filter.The harmonic filter accepts as input signals the in-phase signal and thequadrature signal provided by the poly-phase filter.

[0006] In another embodiment, according to the invention, an RFapparatus includes receive-path circuitry. The receive-path circuitryincludes a harmonic filter followed by a poly-phase filter. The harmonicfilter accepts an input signal (such as a local oscillator signal or abuffered local oscillator signal) and provides an in-phase signal and aquadrature signal. The poly-phase filter couples to the harmonic, filterand accepts as input signals the in-phase signal and the quadraturesignal provided by the harmonic.

[0007] Another aspect of the invention relates to methods of generatingquadrature signals. In one embodiment, a method according to theinvention includes filtering an input signal in a poly-phase filter, andgenerating an in-phase signal and a quadrature signal. The methodfurther includes filtering the in-phase signal and the quadrature signalin a harmonic filter.

DESCRIPTION OF THE DRAWINGS

[0008] The appended drawings illustrate only exemplary embodiments ofthe invention and therefore do not limit its scope. The disclosedinventive concepts lend themselves to other equally effectiveembodiments. In the drawings, the same numerals used in more than onedrawing denote the same, similar, or equivalent functionality,components, or blocks.

[0009]FIG. 1 illustrates the block diagram of an RF transceiver thatincludes radio circuitry that operates in conjunction with a basebandprocessor circuitry.

[0010]FIG. 2A shows RF transceiver circuitry partitioned according tothe invention.

[0011]FIG. 2B depicts another embodiment of RF transceiver circuitrypartitioned according to the invention, in which the reference generatorcircuitry resides within the same circuit partition, or circuit block,as does the receiver digital circuitry.

[0012]FIG. 2C illustrates yet another embodiment of RF transceivercircuitry partitioned according to invention, in which the referencegenerator circuitry resides within the baseband processor circuitry.

[0013]FIG. 2D shows another embodiment of RF transceiver circuitrypartitioned according to the invention, in which the receiver digitalcircuitry resides within the baseband processor circuitry.

[0014]FIG. 3 illustrates interference mechanisms among the variousblocks of an RF transceiver, which the embodiments of the invention inFIGS. 2A-2D, depicting RF transceivers partitioned according to theinvention, seek to overcome, reduce, or minimize.

[0015]FIG. 4 shows a more detailed block diagram of RF transceivercircuitry partitioned according to the invention.

[0016]FIG. 5 illustrates an alternative technique for partitioning RFtransceiver circuitry.

[0017]FIG. 6 shows yet another alternative technique for partitioning RFtransceiver circuitry.

[0018]FIG. 7 depicts a more detailed block diagram of RF transceivercircuitry partitioned according to the invention, in which the receiverdigital circuitry resides within the baseband processor circuitry.

[0019]FIG. 8 illustrates a more detailed block diagram of a multi-bandRF transceiver circuitry partitioned according to the invention.

[0020]FIG. 9A shows a block diagram of an embodiment of the interfacebetween the receiver digital circuitry and receiver analog circuitry inan RF transceiver according to the invention.

[0021]FIG. 9B depicts a block diagram of another embodiment of theinterface between the baseband processor circuitry and the receiveranalog circuitry in an RF transceiver according to the invention, inwhich the receiver digital circuitry resides within the basebandprocessor circuitry.

[0022]FIG. 10 illustrates a more detailed block diagram of the interfacebetween the receiver analog circuitry and the receiver digitalcircuitry, with the interface configured as a serial interface.

[0023]FIG. 11A shows a more detailed block diagram of an embodiment ofthe interface between the receiver analog circuitry and the receiverdigital circuitry, with the interface configured as a data and clocksignal interface.

[0024]FIG. 11B illustrates a block diagram of an embodiment of adelay-cell circuitry that includes a clock driver circuitry in tandemwith a clock receiver circuitry.

[0025]FIG. 12 depicts a schematic diagram of an embodiment of asignal-driver circuitry used to interface the receiver analog circuitryand the receiver digital circuitry according to the invention.

[0026]FIGS. 13A and 13B illustrate schematic diagrams of embodiments ofsignal-receiver circuitries used to interface the receiver analogcircuitry and the receiver digital circuitry according to the invention.

[0027]FIG. 14 shows a schematic diagram of another signal-drivercircuitry that one may use to interface the receiver analog circuitryand the receiver digital circuitry according to the invention.

[0028]FIG. 15 depicts a block diagram of a portion of receive-pathcircuitry in a low-IF or direct conversion RF receiver.

[0029]FIG. 16 illustrates a quadrature-generation circuit that uses apoly-phase filter to generate quadrature signals.

[0030]FIG. 17 shows a plot versus frequency of the magnitude of atransfer function of a poly-phase filter used to generate quadraturesignals.

[0031]FIG. 18 depicts a spectrum of the output of the poly-phase filtershown in FIG. 16 and used to generate quadrature signals.

[0032]FIG. 19 illustrates a graphical representation of the folding overof the frequency component present at the third harmonic frequency tothe positive fundamental frequency.

[0033]FIG. 20 shows a circuit arrangement for improved quadrature signalgeneration according to an illustrative embodiment of the invention.

[0034]FIG. 21 depicts an illustrative embodiment of a harmonic filteraccording to the invention.

[0035]FIG. 22 illustrates an illustrative embodiment of another harmonicfilter according to the invention.

[0036]FIG. 23 shows a plot versus frequency of the magnitude of atransfer function of the poly-phase filter and the harmonic filter.

[0037]FIG. 24 depicts an illustrative embodiment of another harmonicfilter according to the invention.

[0038]FIG. 25 illustrates an illustrative embodiment of animplementation of an active harmonic filter (and corresponding limiter)according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0039] This invention in part contemplates partitioning RF apparatus soas to provide highly integrated, high-performance, low-cost, and lowform-factor RF solutions. One may use RF apparatus according to theinvention in high-performance communication systems. More particularly,the invention in part relates to partitioning RF receiver or transceivercircuitry in a way that minimizes, reduces, or overcomes interferenceeffects among the various blocks of the RF receiver or transceiver,while simultaneously satisfying the requirements of the standards thatgovern RF receiver or transceiver performance. Those standards includethe Global System for Mobile (GSM) communication, Personal CommunicationServices (PCS), Digital Cellular System (DCS), Enhanced Data for GSMEvolution (EDGE), and General Packet Radio Services (GPRS). RF receiveror transceiver circuitry partitioned according to the inventiontherefore overcomes interference effects that would be present in highlyintegrated RF receivers or transceivers while meeting the requirementsof the governing standards at low cost and with a low form-factor. Thedescription of the invention refers to circuit partition and circuitblock interchangeably.

[0040]FIG. 1 shows the general block diagram of an RF transceivercircuitry 100 according to the invention. The RF transceiver circuitry100 includes radio circuitry 110 that couples to an antenna 130 via abi-directional signal path 160. The radio circuitry 110 provides an RFtransmit signal to the antenna 130 via the bi-directional signal path160 when the transceiver is in transmit mode. When in the receive mode,the radio circuitry 110 receives an RF signal from the antenna 130 viathe bi-directional signal path 160.

[0041] The radio circuitry 110 also couples to a baseband processorcircuitry 120. The baseband processor circuitry 120 may comprise adigital-signal processor (DSP). Alternatively, or in addition to theDSP, the baseband processor circuitry 120 may comprise other types ofsignal processor, as persons skilled in the art understand. The radiocircuitry 110 processes the RF signals received from the antenna 130 andprovides receive signals 140 to the baseband processor circuitry 120. Inaddition, the radio circuitry 110 accepts transmit input signals 150from the baseband processor 120 and provides the RF transmit signals tothe antenna 130.

[0042] FIGS. 2A-2D show various embodiments of RF transceiver circuitrypartitioned according to the invention. FIG. 3 and its accompanyingdescription below make clear the considerations that lead to thepartitioning of the RF transceiver circuitry as shown in FIGS. 2A-2D.FIG. 2A illustrates an embodiment 200A of an RF transceiver circuitrypartitioned according to the invention. In addition to the elementsdescribed in connection with FIG. 1, the RF transceiver 200A includesantenna interface circuitry 202, receiver circuitry 210, transmittercircuitry 216, reference generator circuitry 218, and local oscillatorcircuitry 222.

[0043] The reference generator circuitry 218 produces a reference signal220 and provides that signal to the local oscillator circuitry 222 andto receiver digital circuitry 212. The reference signal 220 preferablycomprises a clock signal, although it may include other signals, asdesired. The local oscillator circuitry 222 produces an RF localoscillator signal 224, which it provides to receiver analog circuitry208 and to the transmitter circuitry 216. The local oscillator circuitry222 also produces a transmitter intermediate-frequency (IF) localoscillator signal 226 and provides that signal to the transmittercircuitry 216. Note that, in RF transceivers according to the invention,the receiver analog circuitry 208 generally comprises mostly analogcircuitry in addition to some digital or mixed-mode circuitry, forexample, analog-to-digital converter (ADC) circuitry and circuitry toprovide an interface between the receiver analog circuitry and thereceiver digital circuitry, as described below.

[0044] The antenna interface circuitry 202 facilitates communicationbetween the antenna 130 and the rest of the RF transceiver. Although notshown explicitly, the antenna interface circuitry 202 may include atransmit/receive mode switch, RF filters, and other transceiverfront-end circuitry, as persons skilled in the art understand. In thereceive mode, the antenna interface circuitry 202 provides RF receivesignals 204 to the receiver analog circuitry 208. The receiver analogcircuitry 208 uses the RF local oscillator signal 224 to process (e.g.,down-convert) the RF receive signals 204 and produce a processed analogsignal. The receiver analog circuitry 208 converts the processed analogsignal to digital format and supplies the resulting digital receivesignals 228 to the receiver digital circuitry 212. The receiver digitalcircuitry 212 further processes the digital receive signals 228 andprovides the resulting receive signals 140 to the baseband processorcircuitry 120.

[0045] In the transmit mode, the baseband processor circuitry 120provides transmit input signals 150 to the transmitter circuitry 216.The transmitter circuitry 216 uses the RF local oscillator signal 224and the transmitter IF local oscillator signal 226 to process thetransmit input signals 150 and to provide the resulting transmit RFsignal 206 to the antenna interface circuitry 202. The antenna interfacecircuitry 202 may process the transmit RF signal further, as desired,and provide the resulting signal to the antenna 130 for propagation intoa transmission medium.

[0046] The embodiment 200A in FIG. 2A comprises a first circuitpartition, or circuit block, 214 that includes the receiver analogcircuitry 208 and the transmitter circuitry 216. The embodiment 200Aalso includes a second circuit partition, or circuit block, thatincludes the receiver digital circuitry 212. The embodiment 200A furtherincludes a third circuit partition, or circuit block, that comprises thelocal oscillator circuitry 222. The first circuit partition 214, thesecond circuit partition 212, and the third circuit partition 222 arepartitioned from one another so that interference effects among thecircuit partitions tend to be reduced. The first, second, and thirdcircuit partitions preferably each reside within an integrated circuitdevice. In other words, preferably the receiver analog circuitry 208 andthe transmitter circuitry 216 reside within an integrated circuitdevice, the receiver digital circuitry 212 resides within anotherintegrated circuit device, and the local oscillator circuitry 222resides within a third integrated circuit device.

[0047]FIG. 2B shows an embodiment 200B of an RF transceiver circuitrypartitioned according to the invention. The embodiment 200B has the samecircuit topology as that of embodiment 200A in FIG. 2A. The partitioningof embodiment 200B, however, differs from the partitioning of embodiment200A. Like embodiment 200A, embodiment 200B has three circuitpartitions, or circuit blocks. The first and the third circuitpartitions in embodiment 200B are similar to the first and third circuitpartitions in embodiment 200A. The second circuit partition 230 inembodiment 200B, however, includes the reference signal generator 218 inaddition to the receiver digital circuitry 212. As in embodiment 200A,embodiment 200B is partitioned so that interference effects among thethree circuit partitions tend to be reduced.

[0048]FIG. 2C illustrates an embodiment 200C, which constitutes avariation of embodiment 200A in FIG. 2A. Embodiment 200C shows that onemay place the reference signal generator 218 within the basebandprocessor circuitry 120, as desired. Placing the reference signalgenerator 218 within the baseband processor circuitry 120 obviates theneed for either discrete reference signal generator circuitry 218 or anadditional integrated circuit or module that includes the referencesignal generator 218. Embodiment 200C has the same partitioning asembodiment 200A, and operates in a similar manner.

[0049] Note that FIGS. 2A-2C show the receiver circuitry 210 as a blockto facilitate the description of the embodiments shown in those figures.In other words, the block containing the receiver circuitry 210 in FIGS.2A-2C constitutes a conceptual depiction of the receiver circuitrywithin the RF transceiver shown in FIGS. 2A-2C, not a circuit partitionor circuit block.

[0050]FIG. 2D shows an embodiment 200D of an RF transceiver partitionedaccording to the invention. The RF transceiver in FIG. 2D operatessimilarly to the transceiver shown in FIG. 2A. The embodiment 200D,however, accomplishes additional economy by including the receiverdigital circuitry 212 within the baseband processor circuitry 120. Asone alternative, one may integrate the entire receiver digital circuitry212 on the same integrated circuit device that includes the basebandprocessor circuitry 120. Note that one may use software (or firmware),hardware, or a combination of software (or firmware) and hardware torealize the functions of the receiver digital circuitry 212 within thebaseband processor circuitry 120, as persons skilled in the art who havethe benefit of the description of the invention understand. Note alsothat, similar to the embodiment 200C in FIG. 2C, the baseband processorcircuitry 120 in embodiment 200D may also include the reference signalgenerator 218, as desired.

[0051] The partitioning of embodiment 200D involves two circuitpartitions, or circuit blocks. The first circuit partition 214 includesthe receiver analog circuitry 208 and the transmitter circuitry 216. Thesecond circuit partition includes the local oscillator circuitry 222.The first and second circuit partitions are partitioned so thatinterference effects between them tend to be reduced.

[0052]FIG. 3 shows the mechanisms that may lead to interference amongthe various blocks or components in a typical RF transceiver, forexample, the transceiver shown in FIG. 2A. Note that the paths witharrows in FIG. 3 represent interference mechanisms among the blockswithin the transceiver, rather than desired signal paths. Oneinterference mechanism results from the reference signal 220 (see FIGS.2A-2D), which preferably comprises a clock signal. In the preferredembodiments, the reference generator circuitry produces a clock signalthat may have a frequency of 13 MHz (GSM clock frequency) or 26 MHz. Ifthe reference generator produces a 26 MHz clock signal, RF transceiversaccording to the invention preferably divide that signal by two toproduce a 13 MHz master system clock. The clock signal typicallyincludes voltage pulses that have many Fourier series harmonics. TheFourier series harmonics extend to many multiples of the clock signalfrequency. Those harmonics may interfere with the receiver analogcircuitry 208 (e.g., the low-noise amplifier, or LNA), the localoscillator circuitry 222 (e.g., the synthesizer circuitry), and thetransmitter circuitry 216 (e.g., the transmitter's voltage-controlledoscillator, or VCO). FIG. 3 shows these sources of interference asinterference mechanisms 360, 350, and 340.

[0053] The receiver digital circuitry 212 uses the output of thereference generator circuitry 218, which preferably comprises a clocksignal. Interference mechanism 310 exists because of the sensitivity ofthe receiver analog circuitry 208 to the digital switching noise andharmonics present in the receiver digital circuitry 212. Interferencemechanism 310 may also exist because of the digital signals (forexample, clock signals) that the receiver digital circuitry 212communicates to the receiver analog circuitry 208. Similarly, thedigital switching noise and harmonics in the receiver digital circuitry212 may interfere with the local oscillator circuitry 222, giving riseto interference mechanism 320 in FIG. 3.

[0054] The local oscillator circuitry 222 typically uses an inductor inan inductive-capacitive (LC) resonance tank (not shown explicitly in thefigures). The resonance tank may circulate relatively large currents.Those currents may couple to the sensitive circuitry within thetransmitter circuitry 216 (e.g., the transmitter's VCO), thus givingrise to interference mechanism 330. Similarly, the relatively largecurrents circulating within the resonance tank of the local oscillatorcircuitry 222 may saturate sensitive components within the receiveranalog circuitry 208 (e.g., the LNA circuitry). FIG. 3 depicts thisinterference source as interference mechanism 370.

[0055] The timing of the transmit mode and receive mode in the GSMspecifications help to mitigate potential interference between thetransceiver's receive-path circuitry and its transmit-path circuitry.The GSM specifications use time-division duplexing (TDD). According tothe TDD protocol, the transceiver deactivates the transmit-pathcircuitry while in the receive mode of operation, and vice-versa.Consequently, FIG. 3 does not show potential interference mechanismsbetween the transmitter circuitry 216 and either the receiver digitalcircuitry 212 or the receiver analog circuitry 208.

[0056] As FIG. 3 illustrates, interference mechanisms exist between thelocal oscillator circuitry 222 and each of the other blocks orcomponents in the RF transceiver. Thus, to reduce interference effects,RF transceivers according to the invention preferably partition thelocal oscillator circuitry 222 separately from the other transceiverblocks shown in FIG. 3. Note, however, that in some circumstances onemay include parts or all of the local oscillator circuitry within thesame circuit partition (for example, circuit partition 214 in FIGS.2A-2D) that includes the receiver analog circuitry and the transmittercircuitry, as desired. Typically, a voltage-controlled oscillator (VCO)within the local oscillator circuitry causes interference with othersensitive circuit blocks (for example, the receiver analog circuitry)through undesired coupling mechanisms. If those coupling mechanisms canbe mitigated to the extent that the performance characteristics of theRF transceiver are acceptable in a given application, then one mayinclude the local oscillator circuitry within the same circuit partitionas the receiver analog circuitry and the transmitter circuitry.Alternatively, if the VCO circuitry causes unacceptable levels ofinterference, one may include other parts of the local oscillatorcircuitry within the circuit partition that includes the receiver analogcircuitry and the transmitter circuitry, but exclude the VCO circuitryfrom that circuit partition.

[0057] To reduce the effects of interference mechanism 310, RFtransceivers according to the invention partition the receiver analogcircuitry 208 separately from the receiver digital circuitry 212.Because of the mutually exclusive operation of the transmitter circuitry216 and the receiver analog circuitry 208 according to GSMspecifications, the transmitter circuitry 216 and the receiver analogcircuitry 208 may reside within the same circuit partition, or circuitblock. Placing the transmitter circuitry 216 and the receiver analogcircuitry 208 within the same circuit partition results in a moreintegrated RF transceiver overall. The RF transceivers shown in FIGS.2A-2D employ partitioning techniques that take advantage of the aboveanalysis of the interference mechanisms among the various transceivercomponents. To reduce interference effects among the various circuitpartitions or circuit blocks even further, RF transceivers according tothe invention also use differential signals to couple the circuitpartitions or circuit blocks to one another.

[0058]FIG. 4 shows a more detailed block diagram of an embodiment 400 ofan RF transceiver partitioned according to the invention. Thetransceiver includes receiver analog circuitry 408, receiver digitalcircuitry 426, and transmitter circuitry 465. In the receive mode, theantenna interface circuitry 202 provides an RF signal 401 to a filtercircuitry 403. The filter circuitry 403 provides a filtered RF signal406 to the receiver analog circuitry 408. The receiver analog circuitry408 includes down-converter (i.e., mixer) circuitry 409 andanalog-to-digital converter (ADC) circuitry 418. The down-convertercircuitry 409 mixes the filtered RF signal 406 with an RF localoscillator signal 454, received from the local oscillator circuitry 222.The down-converter circuitry 409 provides an in-phase analogdown-converted signal 412 (i.e., I-channel signal) and a quadratureanalog down-converted signal 415 (i.e., Q-channel signal) to the ADCcircuitry 418.

[0059] The ADC circuitry 418 converts the in-phase analog down-convertedsignal 412 and the quadrature analog down-converted signal 415 into aone-bit in-phase digital receive signal 421 and a one-bit quadraturedigital receive signal 424. (Note that FIGS. 4-8 illustrate signal flow,rather than specific circuit implementations; for more details of thecircuit implementation, for example, more details of the circuitryrelating to the one-bit in-phase digital receive signal 421 and theone-bit quadrature digital receive signal 424, see FIGS. 9-14.) Thus,The ADC circuitry 418 provides the one-bit in-phase digital receivesignal 421 and the one-bit quadrature digital receive signal 424 to thereceiver digital circuitry 426. As described below, rather than, or inaddition to, providing the one-bit in-phase and quadrature digitalreceive signals to the receiver digital circuitry 426, the digitalinterface between the receiver analog circuitry 408 and the receiverdigital circuitry 426 may communicate various other signals. By way ofillustration, those signals may include reference signals (e.g., clocksignals), control signals, logic signals, hand-shaking signals, datasignals, status signals, information signals, flag signals, and/orconfiguration signals. Moreover, the signals may constitute single-endedor differential signals, as desired. Thus, the interface provides aflexible communication mechanism between the receiver analog circuitryand the receiver digital circuitry.

[0060] The receiver digital circuitry 426 includes digitaldown-converter circuitry 427, digital filter circuitry 436, anddigital-to-analog converter (DAC) circuitry 445. The digitaldown-converter circuitry 427 accepts the one-bit in-phase digitalreceive signal 421 and the one-bit quadrature digital receive signal 424from the receiver analog circuitry 408. The digital down-convertercircuitry 427 converts the received signals into a down-convertedin-phase signal 430 and a down-converted quadrature signal 433 andprovides those signals to the digital filter circuitry 436. The digitalfilter circuitry 436 preferably comprises an infinite impulse response(IIR) channel-select filter that performs various filtering operationson its input signals. The digital filter circuitry 436 preferably hasprogrammable response characteristics. Note that, rather than using anIIR filter, one may use other types of filter (e.g., finiteimpulse-response, or FIR, filters) that provide fixed or programmableresponse characteristics, as desired.

[0061] The digital filter circuitry 436 provides a digital in-phasefiltered signal 439 and a digital quadrature filtered signal 442 to theDAC circuitry 445. The DAC circuitry 445 converts the digital in-phasefiltered signal 439 and the digital quadrature filtered signal 442 to anin-phase analog receive signal 448 and a quadrature analog receivesignal 451, respectively. The baseband processor circuitry 120 acceptsthe in-phase analog receive signal 448 and the quadrature analog receivesignal 451 for further processing.

[0062] The transmitter circuitry 465 comprises baseband up-convertercircuitry 466, offset phase-lock-loop (PLL) circuitry 472, and transmitvoltage-controlled oscillator (VCO) circuitry 481. The transmit VCOcircuitry 481 typically has low-noise circuitry and is sensitive toexternal noise. For example, it may pick up interference from digitalswitching because of the high gain that results from the resonantLC-tank circuit within the transmit VCO circuitry 481. The basebandup-converter circuitry 466 accepts an intermediate frequency (IF) localoscillator signal 457 from the local oscillator circuitry 222. Thebaseband up-converter circuitry 466 mixes the IF local oscillator signal457 with an analog in-phase transmit input signal 460 and an analogquadrature transmit input signal 463 and provides an up-converted IFsignal 469 to the offset PLL circuitry 472.

[0063] The offset PLL circuitry 472 effectively filters the IF signal469. In other words, the offset PLL circuitry 472 passes through itsignals within its bandwidth but attenuates other signals. In thismanner, the offset PLL circuitry 472 attenuates any spurious or noisesignals outside its bandwidth, thus reducing the requirement forfiltering at the antenna 130, and reducing system cost, insertion loss,and power consumption. The offset PLL circuitry 472 forms a feedbackloop with the transmit VCO circuitry 481 via an offset PLL output signal475 and a transmit VCO output signal 478. The transmit VCO circuitry 481preferably has a constant-amplitude output signal.

[0064] The offset PLL circuitry 472 uses a mixer (not shown explicitlyin FIG. 4) to mix the RF local oscillator signal 454 with the transmitVCO output signal 478. Power amplifier circuitry 487 accepts thetransmit VCO output signal 478, and provides an amplified RF signal 490to the antenna interface circuitry 202. The antenna interface circuitry202 and the antenna 130 operate as described above. RF transceiversaccording to the invention preferably use transmitter circuitry 465 thatcomprises analog circuitry, as shown in FIG. 4. Using such circuitryminimizes interference with the transmit VCO circuitry 481 and helps tomeet emission specifications for the transmitter circuitry 465.

[0065] The receiver digital circuitry 426 also accepts the referencesignal 220 from the reference generator circuitry 218. The referencesignal 220 preferably comprises a clock signal. The receiver digitalcircuitry 426 provides to the transmitter circuitry 465 a switchedreference signal 494 by using a switch 492. Thus, the switch 492 mayselectively provide the reference signal 220 to the transmittercircuitry 465. Before the RF transceiver enters its transmit mode, thereceiver digital circuitry 426 causes the switch 492 to close, thusproviding the switched reference signal 494 to the transmitter circuitry465.

[0066] The transmitter circuitry 465 uses the switched reference signal494 to calibrate or adjust some of its components. For example, thetransmitter circuitry 465 may use the switched reference signal 494 tocalibrate some of its components, such as the transmit VCO circuitry481, for example, as described in commonly owned U.S. Pat. No.6,137,372, incorporated by reference here in its entirety. Thetransmitter circuitry 465 may also use the switched reference signal 494to adjust a voltage regulator within its output circuitry so as totransmit at known levels of RF radiation or power.

[0067] While the transmitter circuitry 465 calibrates and adjusts itscomponents, the analog circuitry within the transmitter circuitry 465powers up and begins to settle. When the transmitter circuitry 465 hasfinished calibrating its internal circuitry, the receiver digitalcircuitry 426 causes the switch 492 to open, thus inhibiting the supplyof the reference signal 220 to the transmitter circuitry 465. At thispoint, the transmitter circuitry may power up the power amplifiercircuitry 487 within the transmitter circuitry 465. The RF transceiversubsequently enters the transmit mode of operation and proceeds totransmit.

[0068] Note that FIG. 4 depicts the switch 492 as a simple switch forconceptual, schematic purposes. One may use a variety of devices torealize the function of the controlled switch 492, for example,semiconductor switches, gates, or the like, as persons skilled in theart who have the benefit of the disclosure of the invention understand.Note also that, although FIG. 4 shows the switch 492 as residing withinthe receiver digital circuitry 426, one may locate the switch in otherlocations, as desired. Placing the switch 492 within the receiverdigital circuitry 426 helps to confine to the receiver digital circuitry426 the harmonics that result from the switching circuitry.

[0069] The embodiment 400 in FIG. 4 comprises a first circuit partition407, or circuit block, that includes the receiver analog circuitry 408and the transmitter circuitry 465. The embodiment 400 also includes asecond circuit partition, or circuit block, that includes the receiverdigital circuitry 426. Finally, the embodiment 400 includes a thirdcircuit partition, or circuit block, that comprises the local oscillatorcircuitry 222. The first circuit partition 407, the second circuitpartition, and the third circuit partition are partitioned from oneanother so that interference effects among the circuit partitions tendto be reduced. That arrangement tends to reduce the interference effectsamong the circuit partitions by relying on the analysis of interferenceeffects provided above in connection with FIG. 3. Preferably, the first,second, and third circuit partitions each reside within an integratedcircuit device. To further reduce interference effects among the circuitpartitions, the embodiment 400 in FIG. 4 uses differential signalswherever possible. The notation “(diff.)” adjacent to signal lines orreference numerals in FIG. 4 denotes the use of differential lines topropagate the annotated signals.

[0070] Note that the embodiment 400 shown in FIG. 4 uses ananalog-digital-analog signal path in its receiver section. In otherwords, the ADC circuitry 418 converts analog signals into digitalsignals for further processing, and later conversion back into analogsignals by the DAC circuitry 445. RF transceivers according to theinvention use this particular signal path for the following reasons.First, the ADC circuitry 418 obviates the need for propagating signalsfrom the receiver analog circuitry 408 to the receiver digital circuitry426 over an analog interface with a relatively high dynamic range. Thedigital interface comprising the one-bit in-phase digital receive signal421 and the one-bit quadrature digital receive signal 424 is lesssusceptible to the effects of noise and interference than would be ananalog interface with a relatively high dynamic range.

[0071] Second, the RF transceiver in FIG. 4 uses the DAC circuitry 445to maintain compatibility with interfaces commonly used to communicatewith baseband processor circuitry in RF transceivers. According to thoseinterfaces, the baseband processor accepts analog, rather than digital,signals from the receive path circuitry within the RF transceiver. In anRF transceiver that meets the specifications of those interfaces, thereceiver digital circuitry 426 would provide analog signals to thebaseband processor circuitry 120. The receiver digital circuitry 426uses the DAC circuitry 445 to provide analog signals (i.e., the in-phaseanalog receive signal 448 and the quadrature analog receive signal 451)to the baseband processor circuitry 120. The DAC circuitry 445 allowsprogramming the common-mode level and the full-scale voltage, which mayvary among different baseband processor circuitries.

[0072] Third, compared to an analog solution, the analog-digital-analogsignal path may result in reduced circuit size and area (for example,the area occupied within an integrated circuit device), thus lower cost.Fourth, the digital circuitry provides better repeatability, relativeease of testing, and more robust operation than its analog counterpart.Fifth, the digital circuitry has less dependence on supply voltagevariation, temperature changes, and the like, than does comparableanalog circuitry.

[0073] Sixth, the baseband processor circuitry 120 typically includesprogrammable digital circuitry, and may subsume the functionality of thedigital circuitry within the receiver digital circuitry 426, if desired.Seventh, the digital circuitry allows more precise signal processing,for example, filtering, of signals within the receive path. Eighth, thedigital circuitry allows more power-efficient signal processing.Finally, the digital circuitry allows the use of readily programmableDAC circuitry and PGA circuitry that provide for more flexibleprocessing of the signals within the receive path. To benefit from theanalog-digital-analog signal path, RF transceivers according to theinvention use a low-IF signal (for example, 100 KHz for GSMapplications) in their receive path circuitry, as using higher IFfrequencies may lead to higher performance demands on the ADC and DACcircuitry within that path. The low-IF architecture also easesimage-rejection requirements, and allows on-chip integration of thedigital filter circuitry 436. Moreover, RF transceivers according to theinvention use the digital down-converter circuitry 427 and the digitalfilter circuitry 436 to implement a digital-IF path in the receivesignal path. The digital-IF architecture facilitates the implementationof the digital interface between the receiver digital circuitry 426 andthe receiver analog circuitry 408.

[0074] If the receiver digital circuitry 426 need not be compatible withthe common analog interface to baseband processors, one may remove theDAC circuitry 445 and use a digital interface to the baseband processorcircuitry 120, as desired. In fact, similar to the RF transceiver shownin FIG. 2D, one may realize the function of the receiver digitalcircuitry 426 within the baseband processor circuitry 120, usinghardware, software, or a combination of hardware and software. In thatcase, the RF transceiver would include two circuit partitions, orcircuit blocks. The first circuit partition, or circuit block, 407 wouldinclude the receiver analog circuitry 408 and the transmitter circuitry465. A second circuit partition, or circuit block, would comprise thelocal oscillator circuitry 222. Note also that, similar to the RFtransceiver shown in FIG. 2C, one may include within the basebandprocessor circuitry 120 the functionality of the reference generatorcircuitry 218, as desired.

[0075] One may partition the RF transceiver shown in FIG. 4 in otherways. FIGS. 5 and 6 illustrate alternative partitioning of the RFtransceiver of FIG. 4. FIG. 5 shows an embodiment 500 of an RFtransceiver that includes three circuit partitions, or circuit blocks. Afirst circuit partition includes the receiver analog circuitry 408. Asecond circuit partition 505 includes the receiver digital circuitry 426and the transmitter circuitry 465. As noted above, the GSMspecifications provide for alternate operation of RF transceivers inreceive and transmit modes. The partitioning shown in FIG. 5 takesadvantage of the GSM specifications by including the receiver digitalcircuitry 426 and the transmitter circuitry 465 within the secondcircuit partition 505. A third circuit partition includes the localoscillator circuitry 222. Preferably, the first, second, and thirdcircuit partitions each reside within an integrated circuit device.Similar to embodiment 400 in FIG. 4, the embodiment 500 in FIG. 5 usesdifferential signals wherever possible to further reduce interferenceeffects among the circuit partitions.

[0076]FIG. 6 shows another alternative partitioning of an RFtransceiver. FIG. 6 shows an embodiment 600 of an RF transceiver thatincludes three circuit partitions, or circuit blocks. A first circuitpartition 610 includes part of the receiver analog circuitry, i.e., thedown-converter circuitry 409, together with the transmitter circuitry465. A second circuit partition 620 includes the ADC circuitry 418,together with the receiver digital circuitry, i.e., the digitaldown-converter circuitry 427, the digital filter circuitry 436, and theDAC circuitry 445. A third circuit partition includes the localoscillator circuitry 222. Preferably, the first, second, and thirdcircuit partitions each reside within an integrated circuit device.Similar to embodiment 400 in FIG. 4, the embodiment 600 in FIG. 6 usesdifferential signals wherever possible to further reduce interferenceeffects among the circuit partitions.

[0077]FIG. 7 shows a variation of the RF transceiver shown in FIG. 4.FIG. 7 illustrates an embodiment 700 of an RF transceiver partitionedaccording to the invention. Note that, for the sake of clarity, FIG. 7does not explicitly show the details of the receiver analog circuitry408, the transmitter circuitry 465, and the receiver digital circuitry426. The receiver analog circuitry 408, the transmitter circuitry 465,and the receiver digital circuitry 426 include circuitry similar tothose shown in their corresponding counterparts in FIG. 4. Similar tothe RF transceiver shown in FIG. 2D, the embodiment 700 in FIG. 7 showsan RF transceiver in which the baseband processor 120 includes thefunction of the receiver digital circuitry 426. The baseband processorcircuitry 120 may realize the function of the receiver digital circuitry426 using hardware, software, or a combination of hardware and software.

[0078] Because the embodiment 700 includes the function of the receiverdigital circuitry 426 within the baseband processor circuitry 120, itincludes two circuit partitions, or circuit blocks. A first circuitpartition 710 includes the receiver analog circuitry 408 and thetransmitter circuitry 465. A second circuit partition comprises thelocal oscillator circuitry 222. Note also that, similar to the RFtransceiver shown in FIG. 2C, one may also include within the basebandprocessor circuitry 120 the functionality of the reference generatorcircuitry 218, as desired.

[0079]FIG. 8 shows an embodiment 800 of a multi-band RF transceiver,partitioned according to the invention. Preferably, the RF transceiverin FIG. 8 operates within the GSM (925 to 960 MHz for reception and880-915 MHz for transmission), PCS (1930 to 1990 MHz for reception and1850-1910 MHz for transmission), and DCS (1805 to 1880 MHz for receptionand 1710-1785 MHz for transmission) bands. Like the RF transceiver inFIG. 4, the RF transceiver in FIG. 8 uses a low-IF architecture. Theembodiment 800 includes receiver analog circuitry 839, receiver digitalcircuitry 851, transmitter circuitry 877, local oscillator circuitry222, and reference generator circuitry 218. The local oscillatorcircuitry 222 includes RF phase-lock loop (PLL) circuitry 840 andintermediate-frequency (IF) PLL circuitry 843. The RF PLL circuitry 840produces the RF local oscillator, or RF LO, signal 454, whereas the IFPLL circuitry 843 produces the IF local oscillator, or IF LO, signal457.

[0080] Table 1 below shows the preferred frequencies for the RF localoscillator signal 454 during the receive mode: TABLE RF Local OscillatorBand Frequency (MHz) GSM 1849.8-1919.8 DCS 1804.9-1879.9 PCS1929.9-1989.9 All 1804.9-1989.9 Bands

[0081] Table 2 below lists the preferred frequencies for the RF localoscillator signal 454 during the transmit mode: TABLE 2 RF LocalOscillator Band Frequency (MHz) GSM 1279-1314 DCS 1327-1402 PCS1423-1483 All 1279-1483 Bands

[0082] During the receive mode, the IF local oscillator signal 457 ispreferably turned off. In preferred embodiments, during the transmitmode, the IF local oscillator signal 457 preferably has a frequencybetween 383 MHz and 427 MHz. Note, however, that one may use otherfrequencies for the RF and IF local oscillator signals 454 and 457, asdesired.

[0083] The reference generator 218 provides a reference signal 220 thatpreferably comprises a clock signal, although one may use other signals,as persons skilled in the art who have the benefit of the description ofthe invention understand. Moreover, the transmitter circuitry 877preferably uses high-side injection for the GSM band and low-sideinjection for the DCS and PCS bands.

[0084] The receive path circuitry operates as follows. Filter circuitry812 accepts a GSM RF signal 803, a DCS RF signal 806, and a PCS RFsignal 809 from the antenna interface circuitry 202. The filtercircuitry 812 preferably contains a surface-acoustic-wave (SAW) filterfor each of the three bands, although one may use other types andnumbers of filters, as desired. The filter circuitry 812 provides afiltered GSM RF signal 815, a filtered DCS RF signal 818, and a filteredPCS RF signal 821 to low-noise amplifier (LNA) circuitry 824. The LNAcircuitry 824 preferably has programmable gain, and in part provides forprogrammable gain in the receive path circuitry.

[0085] The LNA circuitry 824 provides an amplified RF signal 827 todown-converter circuitry 409. In exemplary embodiments according to theinvention, amplified RF signal 827 includes multiple signal lines, whichmay be differential signal lines, to accommodate the GSM, DCS, and PCSbands. Note that, rather than using the LNA circuitry with a realoutput, one may use an LNA circuitry that has complex outputs (in-phaseand quadrature outputs), together with a poly-phase filter circuitry.The combination of the complex LNA circuitry and the poly-phase filtercircuitry provides better image rejection, albeit with a somewhat higherloss. Thus, the choice of using the complex LNA circuitry and thepoly-phase filter circuitry depends on a trade-off between imagerejection and loss in the poly-phase filter circuitry.

[0086] The down-converter circuitry 409 mixes the amplified RF signal827 with the RF local oscillator signal 454, which it receives from theRF PLL circuitry 840. The down-converter circuitry 409 produces thein-phase analog down-converted signal 412 and the quadrature in-phaseanalog down-converted signal 415. The down-converter circuitry 409provides the in-phase analog down-converted signal 412 and thequadrature in-phase analog down-converted signal 415 to a pair ofprogrammable-gain amplifiers (PGAs) 833A and 833B.

[0087] The PGA 833A and PGA 833B in part allow for programming the gainof the receive path. The PGA 833A and the PGA 833B supply an analogin-phase amplified signal 841 and an analog quadrature amplified signal842 to complex ADC circuitry 836 (i.e., both I and Q inputs will affectboth I and Q outputs). The ADC circuitry 836 converts the analogin-phase amplified signal 841 into a one-bit in-phase digital receivesignal 421. Likewise, the ADC circuitry 836 converts the analogquadrature amplifier signal 842 into a one-bit quadrature digitalreceive signal 424.

[0088] Note that RF transceivers and receivers according to theinvention preferably use a one-bit digital interface. One may, however,use a variety of other interfaces, as persons skilled in the art whohave the benefit of the description of the invention understand. Forexample, one may use a multi-bit interface or a parallel interface.Moreover, as described below, rather than, or in addition to, providingthe one-bit in-phase and quadrature digital receive signals to thereceiver digital circuitry 851, the digital interface between thereceiver analog circuitry 839 and the receiver digital circuitry 851 maycommunicate various other signals. By way of illustration, those signalsmay include reference signals (e.g., clock signals), control signals,logic signals, hand-shaking signals, data signals, status signals,information signals, flag signals, and/or configuration signals.Furthermore, the signals may constitute single-ended or differentialsignals, as desired. Thus, the interface provides a flexiblecommunication mechanism between the receiver analog circuitry and thereceiver digital circuitry.

[0089] The receiver digital circuitry 851 accepts the one-bit in-phasedigital receive signal 421 and the one-bit quadrature digital receivesignal 424, and provides them to the digital down-converter circuitry427. The digital down-converter circuitry 427 converts the receivedsignals into a down-converted in-phase signal 430 and a down-convertedquadrature signal 433 and provides those signals to the digital filtercircuitry 436. The digital filter circuitry 436 preferably comprises anIIR channel-select filter that performs filtering operations on itsinput signals. Note, however, that one may use other types of filters,for example, FIR filters, as desired.

[0090] The digital filter circuitry 436 provides the digital in-phasefiltered signal 439 to a digital PGA 863A and the digital quadraturefiltered signal 442 to a digital PGA 863B. The digital PGA 863A and PGA863B in part allow for programming the gain of the receive pathcircuitry. The digital PGA 863A supplies an amplified digital in-phasesignal 869 to DAC circuitry 875A, whereas the digital PGA 863B suppliesan amplified digital quadrature signal 872 to DAC circuitry 875B. TheDAC circuitry 875A converts the amplified digital in-phase signal 869 tothe in-phase analog receive signal 448. The DAC circuitry 875B convertsthe amplified digital quadrature signal 872 signal into the quadratureanalog receive signal 451. The baseband processor circuitry 120 acceptsthe in-phase analog receive signal 448 and the quadrature analog receivesignal 451 for further processing, as desired.

[0091] Note that the digital circuit blocks shown in the receiverdigital circuitry 851 depict mainly the conceptual functions and signalflow. The actual digital-circuit implementation may or may not containseparately identifiable hardware for the various functional blocks. Forexample, one may re-use (in time, for instance, by using multiplexing)the same digital circuitry to implement both digital PGA 863A anddigital PGA 863B, as desired.

[0092] Note also that, similar to the RF transceiver in FIG. 4, the RFtransceiver in FIG. 8 features a digital-IF architecture. The digital-IFarchitecture facilitates the implementation of the one-bit digitalinterface between the receiver digital circuitry 426 and the receiveranalog circuitry 408. Moreover, the digital-IF architecture allowsdigital (rather than analog) IF-filtering, thus providing all of theadvantages of digital filtering.

[0093] The transmitter circuitry 877 comprises baseband up-convertercircuitry 466, transmit VCO circuitry 481, a pair of transmitter outputbuffers 892A and 892B, and offset PLL circuitry 897. The offset PLLcircuitry 897 includes offset mixer circuitry 891, phase detectorcircuitry 882, and loop filter circuitry 886. The baseband up-convertercircuitry 466 accepts the analog in-phase transmit input signal 460 andthe analog quadrature transmit input signal 463, mixes those signalswith the IF local oscillator signal 457, and provides a transmit IFsignal 880 to the offset PLL circuitry 897. The offset PLL circuitry 897uses the transmit IF signal 880 as a reference signal. The transmit IFsignal 880 preferably comprises a modulated single-sideband IF signalbut, as persons skilled in the art who have the benefit of thedescription of the invention understand, one may use other types ofsignal and modulation, as desired.

[0094] The offset mixer circuitry 891 in the offset PLL circuitry 897mixes the transmit VCO output signal 478 with the RF local oscillatorsignal 454, and provides a mixed signal 890 to the phase detectorcircuitry 882. The phase detector circuitry 882 compares the mixedsignal 890 to the transmit IF signal 880 and provides an offset PLLerror signal 884 to the loop filter circuitry 886. The loop filtercircuitry 886 in turn provides a filtered offset PLL signal 888 to thetransmit VCO circuitry 481. Thus, the offset PLL circuitry 897 and thetransmit VCO circuitry 481 operate in a feedback loop. Preferably, theoutput frequency of the transmit VCO circuitry 481 centers between theDCS and PCS bands, and its output is divided by two for the GSM band.

[0095] Transmitter output buffers 892A and 892B receive the transmit VCOoutput signal 478 and provide buffered transmit signals 894 and 895 to apair of power amplifiers 896A and 896B. The power amplifiers 896A and896B provide amplified RF signals 899 and 898, respectively, fortransmission through antenna interface circuitry 202 and the antenna130. Power amplifier 896A provides the RF signal 899 for the GSM band,whereas power amplifier 896B supplies the RF signal 898 for the DCS andPCS bands. Persons skilled in the art who have the benefit of thedescription of the invention, however, understand that one may use otherarrangements of power amplifiers and frequency bands. Moreover, one mayuse RF filter circuitry within the output path of the transmittercircuitry 877, as desired.

[0096] The embodiment 800 comprises three circuit partitions, or circuitblocks. A first circuit partition 801 includes the receiver analogcircuitry 839 and the transmitter circuitry 877. A second circuitpartition 854 includes the receiver digital circuitry 851 and thereference generator circuitry 218. Finally, a third circuit partitioncomprises the local oscillator circuitry 222. The first circuitpartition 801, the second circuit partition 854, and the third circuitpartition are partitioned from one another so that interference effectsamong the circuit partitions tend to be reduced. That arrangement tendsto reduce the interference effects among the circuit partitions becauseof the analysis of interference effects provided above in connectionwith FIG. 3. Preferably, the first, second, and third circuit partitionseach reside within an integrated circuit device. To further reduceinterference effects among the circuit partitions, the embodiment 800 inFIG. 8 uses differential signals wherever possible. The notation“(diff.)” adjacent to signal lines or reference numerals in FIG. 8denotes the use of differential lines to propagate the annotatedsignals.

[0097] Note that, similar to the RF transceiver shown in FIG. 4 anddescribed above, the embodiment 800 shown in FIG. 8 uses ananalog-digital-analog signal path in its receiver section. Theembodiment 800 uses this particular signal path for reasons similar tothose described above in connection with the transceiver shown in FIG.4.

[0098] Like the transceiver in FIG. 4, if the receiver digital circuitry851 need not be compatible with the common analog interface to basebandprocessors, one may remove the DAC circuitry 875A and 875B, and use adigital interface to the baseband processor circuitry 120, as desired.In fact, similar to the RF transceiver shown in FIG. 2D, one may realizethe function of the receiver digital circuitry 851 within the basebandprocessor circuitry 120, using hardware, software, or a combination ofhardware and software. In that case, the RF transceiver would includetwo circuit partitions, or circuit blocks. The first circuit partition801 would include the receiver analog circuitry 839 and the transmittercircuitry 877. A second circuit partition would comprise the localoscillator circuitry 222. Note also that, similar to the RF transceivershown in FIG. 2C, in the embodiment 800, one may include within thebaseband processor circuitry 120 the functionality of the referencegenerator circuitry 218, as desired.

[0099] Another aspect of the invention includes a configurable interfacebetween the receiver digital circuitry and the receiver analogcircuitry. Generally, one would seek to minimize digital switchingactivity within the receiver analog circuitry. Digital switchingactivity within the receiver analog circuitry would potentiallyinterfere with the sensitive analog RF circuitry, for example, LNAs, ormixers. As described above, the receiver analog circuitry includesanalog-to-digital circuitry (ADC), which preferably comprisessigma-delta-type ADCs. Sigma-delta ADCs typically use a clock signal attheir output stages that generally has a pulse shape and, thus, containshigh-frequency Fourier series harmonics. Moreover, the ADC circuitryitself produces digital outputs that the receiver digital circuitryuses. The digital switching present at the outputs of the ADC circuitrymay also interfere with sensitive analog circuitry within the receiveranalog circuitry.

[0100] The invention contemplates providing RF apparatus according tothe invention, for example, receivers and transceivers, that include aninterface circuitry to minimize or reduce the effects of interferencefrom digital circuitry within the RF apparatus. FIG. 9A shows anembodiment 900A of an interface between the receiver digital circuitry905 and the receiver analog circuitry 910. The interface includesconfigurable interface signal lines 945. The baseband processorcircuitry 120 in the transceiver of FIG. 9A communicates configuration,status, and setup information with both the receiver digital circuitry905 and the receiver analog circuitry 910. In the preferred embodimentsof RF transceivers according to the invention, the baseband processorcircuitry 120 communicates with the receiver digital circuitry 905 andthe receiver analog circuitry 910 by sending configuration data to readand write registers included within the receiver digital circuitry 905and the receiver analog circuitry 910.

[0101] The receiver digital circuitry 905 communicates with the basebandprocessor circuitry 120 through a set of serial interface signal lines920. The serial interface signal lines 920 preferably include a serialdata-in (SDI) signal line 925, a serial clock (SCLK) signal line 930, aserial interface enable (SENB) signal line 935, and a serial data-out(SDO) signal line 940. The transceiver circuitry and the basebandprocessor circuitry 120 preferably hold all of the serial interfacesignal lines 920 at static levels during the transmit and receive modesof operation. The serial interface preferably uses a 22-bit serialcontrol word that comprises 6 address bits and 16 data bits. Note,however, that one may use other serial interfaces, parallel interfaces,or other types of interfaces, that incorporate different numbers ofsignal lines, different types and sizes of signals, or both, as desired.Note also that, the SENB signal is preferably an active-low logicsignal, although one may use a normal (i.e., an active-high) logicsignal by making circuit modifications, as persons skilled in the artunderstand.

[0102] The receiver digital circuitry 905 communicates with the receiveranalog circuitry 910 via configurable interface signal lines 945.Interface signal lines 945 preferably include four configurable signallines 950, 955, 960, and 965, although one may use other numbers ofconfigurable signal lines, as desired, depending on a particularapplication. In addition to supplying the serial interface signals 920,the baseband processor circuitry 120 provides a control signal 915,shown as a power-down (PDNB) signal in FIG. 9A, to both the receiverdigital circuitry 905 and the receiver analog circuitry 910. Thereceiver digital circuitry 905 and the receiver analog circuitry 910preferably use the power-down (PDNB) signal as the control signal 915 toconfigure the functionality of the interface signal lines 945. In otherwords, the functionality of the interface signal lines 945 depends onthe state of the control signal 915. Also, the initialization of thecircuitry within the receive path and the transmit path of thetransceiver occurs upon the rising edge of the PDNB signal. Note thatthe PDNB signal is preferably an active-low logic signal, although onemay use a normal (i.e., an active-high) logic signal, as persons skilledin the art would understand. Note also that, rather than using the PDNBsignal, one may use other signals to control the configuration of theinterface signal lines 945, as desired.

[0103] In the power-down or serial interface mode (i.e., the controlsignal 915 (for example, PDNB) is in the logic low state), interfacesignal line 950 provides the serial clock (SCLK) and interface signalline 955 supplies the serial interface enable signal (SENB).Furthermore, interface signal line 960 provides the serial data-insignal (SDI), whereas interface signal line 965 supplies the serialdata-out (SDO) signal. One may devise other embodiments according to theinvention in which, during this mode of operation, the transceiver mayalso perform circuit calibration and adjustment procedures, as desired(for example, the values of various transceiver components may vary overtime or among transceivers produced in different manufacturing batches.The transceiver may calibrate and adjust its circuitry to take thosevariations into account and provide higher performance).

[0104] In the normal receive mode of operation (i.e., the controlsignal, PDNB, is in the logic-high state), interface signal line 950provides a negative clock signal (CKN) and interface signal line 955supplies the positive clock signal (CKP). Furthermore, interface signalline 960 provides a negative data signal (ION), whereas interface signalline 965 supplies a positive data signal (IOP).

[0105] In preferred embodiments of the invention, the CKN and CKPsignals together form a differential clock signal that the receiverdigital circuitry 905 provides to the receiver analog circuitry 910. Thereceiver analog circuitry 910 may provide the clock signal to thetransmitter circuitry within the RF transceiver in order to facilitatecalibration and adjustment of circuitry, as described above. During thereceive mode, the receiver analog circuitry 910 provides the ION and IOPsignals to the receiver digital circuitry 905. The ION and IOP signalspreferably form a differential data signal. As noted above, thetransceiver disables the transmitter circuitry during the receive modeof operation.

[0106] In preferred embodiments according to the invention, clocksignals CKN and CKP are turned off when the transmitter circuitry istransmitting signals. During the transmit mode, interface signal lines960 and 965 preferably provide two logic signals from the receiverdigital circuitry 905 to the receiver analog circuitry 910. The signallines may provide input/output signals to communicate data, status,information, flag, and configuration signals between the receiverdigital circuitry 905 and the receiver analog circuitry 910, as desired.Preferably, the logic signals control the output buffer of the transmitVCO circuitry. Note that, rather than configuring interface signal lines960 and 965 as logic signal lines, one may configure them in other ways,for example, analog signal lines, differential analog or digital signallines, etc., as desired. Furthermore, the interface signal lines 960 and965 may provide signals from the receiver digital circuitry 905 to thereceiver analog circuitry 910, or vice-versa, as desired.

[0107] In addition to using differential signals, RF transceiversaccording to the invention preferably take other measures to reduceinterference effects among the various transceiver circuits. SignalsCKN, CKP, ION, and IOP may constitute voltage signals, as desired.Depending on the application, the signals CKN, CKP, ION, and IOP (orlogic signals in the transmit mode) may have low voltage swings (forexample, voltage swings smaller than the supply voltage) to reduce themagnitude and effects of interference because of the voltage switchingon those signals.

[0108] In preferred embodiments according to the invention, signals CKN,CKP, ION, and IOP constitute current, rather than voltage, signals.Moreover, to help reduce the effects of interference even further, RFtransceivers according to the invention preferably use band-limitedsignals. RF transceivers according to the invention preferably usefiltering to remove some of the higher frequency harmonics from thosesignals to produce band-limited current signals.

[0109] Table 3 below summarizes the preferred functionality of theconfigurable interface signal lines 950, 955, 960, and 965 as a functionof the state of the control signal 915 (for example, PDNB): TABLE 3Control = 1 Control = 1 (During (During Signal Line Control = 0Reception) Transmission) 950 SCLK CKN (CKN off) 955 SENB CKP (CKP off)960 SDI ION Logic Signal 965 SDO IOP Logic Signal

[0110] Using configurable interface signal lines 945 in the interfacebetween the receiver digital circuitry 905 and the receiver analogcircuitry 910 allows using the same physical connections (e.g., pins onan integrated-circuit device or electrical connectors on a module) toaccomplish different functionality. Thus, the configurable interfacebetween the receiver digital circuitry 905 and the receiver analogcircuitry 910 makes available the physical electrical connectionsavailable for other uses, for example, providing ground pins orconnectors around sensitive analog signal pins or connectors to helpshield those signals from RF interference. Moreover, the configurableinterface between the receiver digital circuitry 905 and the receiveranalog circuitry 910 reduces packaging size, cost, and complexity.

[0111]FIG. 9B shows an embodiment 900B that includes a configurableinterface according to the invention. Here, the baseband processorcircuitry 120 subsumes the functionality of the receiver digitalcircuitry 905. The baseband processor circuitry 120 realizes thefunctionality of the receiver digital circuitry 905, using hardware,software, or both, as desired. Because the baseband processor circuitry120 has subsumed the receiver digital circuitry 905, the basebandprocessor circuitry 120 may communicate with the receiver analogcircuitry 910 using configurable interface signal lines 945, dependingon the state of the control signal 915 (e.g., the PDNB signal). Theconfigurable interface signal lines 945 perform the same functionsdescribed above in connection with FIG. 9A, depending on the state ofthe control signal 915. As noted above, one may reconfigure theinterface signal lines 960 and 965 during transmit mode to implementdesired functionality, for example, logic signals.

[0112]FIG. 10 shows a conceptual block diagram of an embodiment 1000 ofa configurable interface according to the invention within an RFtransceiver in the power-down or serial interface mode (i.e., thecontrol signal 915 is in a logic-low state). A logic low state on thecontrol signal 915 enables the driver circuitry 1012A, 1012B, and 1012C,thus providing the configurable serial interface signal lines 950, 955,and 960 to the receiver analog circuitry 910. Similarly, the logic lowstate on the control signal 915 causes the AND gates 1030A, 1030B, and1030C to provide configurable interface signal lines 950, 955, and 960to other circuitry within the receiver analog circuitry 910. The outputsof the AND gates 1030A, 1030B, and 1030C comprise a gated SCLK signal1032, a gated SENB signal 1034, and a gated SDI signal 1036,respectively.

[0113] Interface controller circuitry 1040 accepts as inputs the gatedSCLK signal 1032, the gated SENB signal 1034, and the gated SDI signal1036. The interface controller circuitry 1040 resides within thereceiver analog circuitry 910 and produces a receiver analog circuitrySDO signal 1044 and an enable signal 1046. By controlling tri-statedriver circuitry 1042, the enable signal 1046 controls the provision ofthe receiver analog circuitry SDO signal 1044 to the receiver digitalcircuitry 905 via the configurable interface signal line 965.

[0114] Interface controller circuitry 1010 within the receiver digitalcircuitry 905 accepts the SCLK signal 925, the SENB signal 930, and theSDI signal 935 from the baseband processor circuitry 120. By decodingthose signals, the interface controller circuitry 1010 determineswhether the baseband processor circuitry 120 intends to communicate withthe receiver digital circuitry 905 (e.g., the baseband processorcircuitry 120 attempts to read a status or control register present onthe receiver digital circuitry 905). If so, the interface controllercircuitry 1010 provides the SCLK signal 925, the SENB signal 930, andthe SDI signal 935 to other circuitry (not shown explicitly) within thereceiver digital circuitry 905 for further processing.

[0115] Interface controller circuitry 1010 provides as output signals areceiver digital circuitry SDO signal 1018, a select signal 1020, and anenable signal 1022. The receiver digital circuitry SDO signal 1018represents the serial data-out signal for the receiver digital circuitry905, i.e., the serial data-out signal that the receiver digitalcircuitry 905 seeks to provide to the baseband processor circuitry 120.The interface controller circuitry 1010 supplies the select signal 1020to multiplexer circuitry 1014. The multiplexer circuitry 1014 uses thatsignal to selectively provide as the multiplexer circuitry output signal1024 either the receiver digital circuitry SDO signal 1018 or thereceiver analog circuitry SDO signal 1044, which it receives throughconfigurable interface signal line 965. Tri-state driver circuitry 1016provides the multiplexer circuitry output signal 1024 to the basebandprocessor circuitry 120 under the control of the enable signal 1022.

[0116] Tri-state driver circuitry 1012A, 1012B, and 1012C use aninverted version of the control signal 915 as their enable signals.Thus, a logic high value on the control signal 915 disables the drivercircuitry 1012A, 1012B, and 1012C, thus disabling the serial interfacebetween the receiver digital circuitry 905 and the receiver analogcircuitry 910. Similarly, AND gates 1030A, 1030B, and 1030C use aninverted version of the control signal 915 to gate interface signallines 950, 955, and 960. In other words, a logic high value on thecontrol signal 915 inhibits logic switching at the outputs of AND gates1030A, 1030B, and 1030C, which reside on the receiver analog circuitry910.

[0117]FIG. 11A shows a conceptual block diagram of an embodiment 1100Aof a configurable interface according to the invention, in an RFtransceiver operating in the normal receive mode of operation (i.e., thecontrol signal 915 is in a logic-high state). As noted above, in thismode, the receiver digital circuitry 905 provides a clock signal to thereceiver analog circuitry 910 through the configurable interface signallines 950 and 955. Configurable interface signal line 950 provides theCKN signal, whereas configurable interface signal line 955 supplies theCKP signal. Also in this mode, the receiver analog circuitry 910provides a data signal to the receiver digital circuitry 905 through theconfigurable interface signal lines 960 and 965.

[0118] The receiver digital circuitry 905 provides the CKN and CKPsignals to the receiver analog circuitry 910 by using clock drivercircuitry 1114. The clock driver circuitry 1114 receives a clock signal1112A and a complement clock signal 1112B from signal processingcircuitry 1110. Signal processing circuitry 1110 receives the referencesignal 220 and converts it to the clock signal 1112A and complementclock signal 1112B. Interface controller circuitry 1116 provides anenable signal 1118 that controls the provision of the CKN and CKP clocksignals to the receiver analog circuitry 910 via the interface signallines 950 and 955, respectively.

[0119] Receiver analog circuitry 910 includes clock receiver circuitry1130 that receives the CKN and CKP clock signals and provides a clocksignal 1132A and a complement clock signal 1132B. Interface controllercircuitry 1140 within the receiver analog circuitry 910 provides anenable signal 1142 that controls the operation of the clock receivercircuitry 1130.

[0120] The clock signal 1132A clocks the ADC circuitry 1144, or othercircuitry (for example, calibration circuitry), or both, as desired.Note that, rather than using the clock signal 1132A, one may use thecomplement clock signal 1132B, or both the clock signal 1132A and thecomplement clock signal 1132B, by making circuit modifications aspersons skilled who have the benefit of the description of the inventionunderstand. The ADC circuitry 1144 provides to multiplexer circuitry1150 a one-bit differential in-phase digital signal 1146A and a one-bitdifferential quadrature digital signal 1146B. The multiplexer circuitry1150 provides a one-bit differential digital output signal 1152 to datadriver circuitry 1154. The output signal 1152 therefore constitutesmultiplexed I-channel data and Q-channel data. The data driver circuitry1154 supplies the differential data signal comprising ION and IOP to thereceiver digital circuitry 905, using the configurable interface signallines 960 and 965, respectively.

[0121] The clock signal 1132A also acts as the select signal ofmultiplexer circuitry 1150. On alternating edges of the clock signal1132A, the multiplexer circuitry 1150 selects, and provides to, the datadriver circuitry 1154 the one-bit differential in-phase digital signal1146A (i.e., I-channel data) and the one-bit differential quadraturedigital signal 1146B (i.e., Q-channel data). The interface controllercircuitry 1140 supplies an enable signal 1156 to the data drivercircuitry 1154 that controls the provision of the configurable interfacesignal 960 and the configurable interface signal 965 to the receiverdigital circuitry 905 via the configurable interface signal lines 960and 965.

[0122] The receiver digital circuitry 905 includes data receivercircuitry 1120. Data receiver circuitry 1120 accepts from the receiveranalog circuitry 910 the signals provided via the configurable interfacesignal lines 960 and 965. The data receiver circuitry 1120 provides apair of outputs 1122A and 1122B. An enable signal 1124, supplied by theinterface controller circuitry 1116, controls the operation of the datareceiver circuitry 1120.

[0123] The receiver digital circuitry 905 also includes a delay-cellcircuitry 1119 that accepts as its inputs the clock signal 1112A and thecomplement clock signal 1112B. The delay-cell circuitry 1119 constitutesa delay-compensation circuit. In other words, ideally, thesignal-propagation delay of the delay-cell circuitry 1119 compensatesfor the delays the signals experience as they propagate from thereceiver digital circuitry 905 to the receiver analog circuitry 910, andback to the receiver digital circuitry 905.

[0124] The delay-cell circuitry 1119 provides as its outputs a clocksignal 1121A and a complement clock signal 1121B. The clock signal 1121Aand the complement clock signal 1121B clock a pair of D flip-flopcircuitries 1123A and 1123B, respectively. The D flip-flop circuitries1123A and 1123B latch the output 1122A of the data receiver circuitry1120 alternately. In other words, the clock signal 1121A causes thelatching of the I-channel data by the D flip-flop circuitry 1123A,whereas the complement clock signal 1121B causes the D flip-flopcircuitry 1123B to latch the Q-channel data.

[0125] The output signals of the delay-cell circuitry 1119 help thereceiver digital circuitry 905 to sample the I-channel data and theQ-channel data that it receives from the receiver analog circuitry 910.The receiver digital circuitry 905 receives multiplexed I-channel dataand the Q-channel data through the ION signal 960 and the IOP signal965. Thus, the D flip-flop circuitries 1123A and 1123B perform ade-multiplexing function on the multiplexed I-channel data and Q-channeldata.

[0126] In the normal receive or transmit modes, (i.e., the controlsignal 915 is in the logic-high state), interface signal line 950provides the negative clock signal (CKN) and interface signal line 955supplies the positive clock signal (CKP). In preferred embodiments ofthe invention, the CKN and CKP signals together form a differentialclock signal that the receiver digital circuitry 905 provides to thereceiver analog circuitry 910.

[0127] During the receive mode, interface signal line 960 provides thenegative data signal (ION), whereas interface signal line 965 suppliesthe positive data signal (IOP). The ION and IOP signals preferably forma differential data signal.

[0128] In the transmit mode, the data signal may function as aninput/output signal to communicate data, status, information, flag,and/or configuration signals between the receiver digital circuitry 905and the receiver analog circuitry 910. Preferably, the interface signallines 960 and 965 function as two logic signal lines in the transmitmode. As noted above, the transceiver disables the receiver circuitryduring the transmit mode of operation. In RF transceivers partitionedaccording to the invention (see, e.g., FIGS. 2A-2D, 4, and 8), the clockreceiver circuitry 1130 may provide the clock signal 1132A, thecomplement clock signal 1132B, or both, to transmitter circuitry(partitioned together with the receiver analog circuitry 910) forcircuit calibration, circuit adjustment, and the like, as describedabove.

[0129] In the transmit mode, once circuit calibration and adjustment hasconcluded, however, the clock driver circuitry 1114 uses the enablesignal 1118 to inhibit the propagation of the CKN and CKP clock signalsto the receiver analog circuitry 910. In this manner, the clock drivercircuitry 1114 performs the function of the switch 492 in FIGS. 4 and 8.Note that, during the normal transmit mode of operation, the ADCcircuitry 1144 does not provide any data to the receiver digitalcircuitry 905 via the ION and IOP signals because, according to the TDDprotocol, the receiver path circuitry is inactive during the normaltransmit mode of operation. Instead, the receiver digital circuitry 905provides control signals to the receiver analog circuitry 910 viainterface signal lines 960 and 965.

[0130] During the transmit mode, the interface controller circuitry 1116provides control signals via signal lines 1160 to the interface signallines 960 and 965. The interface controller circuitry 1140 receives thecontrol signals via signal lines 1165 and provides them to variousblocks within the receiver analog circuitry, as desired. During thereceive mode, the interface controller circuitry 1116 inhibits (e.g.,high-impedance state) the signal lines 1160. Similarly, the interfacecontroller circuitry 1140 inhibits the signal lines 1165 during thereceive mode.

[0131] For the purpose of conceptual illustration, FIG. 11A shows theinterface controller circuitry 1116 and the interface controllercircuitry 1140 as two blocks of circuitry distinct from the interfacecontroller circuitry 1010 and the interface controller circuitry 1040 inFIG. 10, respectively. One may combine the functionality of theinterface controller circuitry 1116 with the functionality of theinterface controller circuitry 1010, as desired. Likewise, one maycombine the functionality of interface controller circuitry 1140 withthe functionality of the interface controller circuitry 1040, asdesired. Moreover, one may combine the functionality of the signalprocessing circuitries 1110 with the functionality of the interfacecontroller circuitry 1116 and the interface controller circuitry 1140,respectively. Combining the functionality of those circuits depends onvarious design and implementation choices, as persons skilled in the artunderstand.

[0132]FIG. 11B illustrates a block diagram of a preferred embodiment1100B of a delay-cell circuitry 1119 according to the invention. Thedelay-cell circuitry 1119 includes a replica of the clock drivercircuitry 1114A in tandem with a replica of the data receiver circuitry1120A. In other words, the block labeled “1114A” is a replica of theclock driver circuitry 1114, and the block labeled “1120A” is a replicaof the data receiver circuitry 1120. (Note that the delay-cell circuitry1119 may alternatively include a replica of the data driver circuitry1154 in tandem with a replica of the clock receiver circuitry 1130.) Thereplica of the clock driver circuitry 1114A accepts the clock signal1112A and the complement clock signal 1112B. The replica of the clockdriver circuitry 1114A provides its outputs to the replica of the datareceiver circuitry 1120A. The replica of the data receiver circuitry1120A supplies the clock signal 1121A and the complement clock signal1121B. The clock signal 1121A and the complement clock signal 1121Bconstitute the output signals of the delay-cell circuitry 1119. Thedelay-cell circuitry 1119 also receives as inputs enable signals 1118and 1124 (note that FIG. 1A does not show those input signals for thesake of clarity). The enable signal 1118 couples to the replica of theclock driver circuitry 1114A, whereas the enable signal 1124 couples tothe replica of the data receiver circuitry 1120A.

[0133] Note that FIG. 11B constitutes a conceptual block diagram of thedelay-cell circuitry 1119. Rather than using distinct blocks 1114A and1120A, one may alternatively use a single block that combines thefunctionality of those two blocks, as desired. Moreover, one may use acircuit that provides an adjustable, rather than fixed, delay, asdesired. Note also that the embodiment 1100B of the delay-cell circuitry1119 preferably compensates for the delay in the clock driver circuitry1114 in FIG. 11A. In other words, the delay-cell circuitry 1119preferably compensates sufficiently for the round-trip delay in thesignals that travel from the receiver digital circuitry 905 to thereceiver analog circuitry 910 and back to the receiver digital circuitry905 to allow for accurate sampling in the receiver digital circuitry ofthe I-channel data and the Q-channel data. Note that in the embodiment1100B, the replica of the clock driver circuitry 1114A mainlycompensates for the round-trip delay, whereas the replica of the datareceiver circuitry 1120A converts low-swing signals at the output of thereplica of the clock driver circuitry 1114A into full-swing signals.

[0134] The receiver digital circuitry 905 and the receiver analogcircuitry 910 preferably reside within separate integrated-circuitdevices. Because those integrated-circuit devices typically result fromseparate semiconductor fabrication processes and manufacturing lines,their process parameters may not match closely. As a result, thepreferred embodiment 1100B of the delay-cell circuitry 1119 does notcompensate for the delay in the clock receiver circuitry 1130, the datadriver circuitry 1154, and the data receiver circuitry 1120 in FIG. 11A.

[0135] Note, however, that if desired, the delay-cell circuitry 1119 mayalso compensate for the signal delays of the clock receiver circuitry1130, the data driver circuitry 1154, and the data receiver circuitry1120. Thus, in situations where one may match the process parameters ofthe receiver digital circuitry 905 and the receiver analog circuitry 910relatively closely (for example, by using thick-film modules,silicon-on-insulator, etc.), the delay-cell circuitry 1119 may alsocompensate for the delays of other circuit blocks. As anotheralternative, one may use a delay-cell circuitry 1119 that provides anadjustable delay and then program the delay based on the delays in thereceiver digital circuitry 905 and the receiver analog circuitry 910(e.g., provide a matched set of receiver digital circuitry 905 andreceiver analog circuitry 910), as persons skilled in the art who havethe benefit of the description of the invention understand. Furthermore,rather than an open-loop arrangement, one may use a closed-loop feedbackcircuit implementation (e.g., by using a phase-locked loop circuitry) tocontrol and compensate for the delay between the receiver analogcircuitry 910 and the receiver digital circuitry 905, as desired.

[0136] Note that the digital circuit blocks shown in FIGS. 11A and 11Bdepict mainly the conceptual functions and signal flow. The actualcircuit implementation may or may not contain separately identifiablehardware for the various functional blocks. For example, one may combinethe functionality of various circuit blocks into one circuit block, asdesired.

[0137]FIG. 12 shows a schematic diagram of a preferred embodiment 1200of a signal-driver circuitry according to the invention. One may use thesignal-driver circuitry as the clock driver circuitry 1114 and the datadriver circuitry 1154 in FIG. 11A. In the latter case, the input signalsto the signal-driver circuitry constitute the output signals 1152 andthe enable signal 1156, whereas the output signals of thesignal-receiver circuitry constitute the ION and IOP signals 960 and965, respectively, in FIG. 11A.

[0138] The signal-driver circuitry in FIG. 12 constitutes two circuitlegs. One circuit leg includes MOSFET devices 1218 and 1227 and resistor1230. The second leg includes MOSFET devices 1242 and 1248 and resistor1251. The input clock signal controls MOSFET devices 1218 and 1242.Current source 1206, MOSFET devices 1209 and 1215, and resistor 1212provide biasing for the two circuit legs.

[0139] MOSFET devices 1227 and 1248 drive the CKN and CKP outputterminals through resistors 1230 and 1251, respectively. Depending onthe state of the clock signal, one leg of the signal-driver circuitryconducts more current than the other leg. Put another way, thesignal-driver circuitry steers current from one leg to the other inresponse to the clock signal (i.e., in response to the clock signal, oneleg of the circuit turns on and the other leg turns off, andvice-versa). As a result, the signal-driver circuitry provides adifferential clock signal that includes current signals CKN and CKP.

[0140] If the enable signal is high, MOSFET device 1203 is off andtherefore does not affect the operation of the rest of the circuit. Inthat case, a current IO flows through the current source 1206 anddiode-connected MOSFET device 1209. The flow of current generates avoltage at the gate of MOSFET device 1209. MOSFET devices 1227 and 1248share the same gate connection with MOSFET device 1209. Thus, MOSFETdevices 1227 and 1248 have the same gate-source voltage, V_(gs), asMOSFET device 1209 when the appropriate MOSFET devices are in the onstate.

[0141] MOSFET devices 1218 and 1242 cause current steering between thefirst and second circuit legs. Only one of the MOSFET devices 1218 and1242 is in the on state during the operation of the circuit. Dependingon which MOSFET device is in the on state, the mirroring current I_(O)flows through the circuit leg that includes the device in the on state.

[0142] Resistors 1221 and 1239 provide a small trickle current to thecircuit leg that includes the MOSFET device (i.e., MOSFET device 1218 orMOSFET device 1242) that is in the off state. The small trickle currentprevents the diode-connected MOSFET devices in the signal receivercircuitry (see FIG. 13) from turning off completely. The trickle currenthelps to reduce the delay in changing the state of the circuit inresponse to transitions in the input clock signal. The trickle currentsalso help to reduce transient signals at the CKP and CKN terminals and,thus, reduce interference effects.

[0143] Capacitors 1224 and 1245 provide filtering so that when MOSFETdevice 1218 and MOSFET device 1242 switch states, the currents throughthe first and second circuit legs (CKN and CKP circuit legs) do notchange rapidly. Thus, capacitors 1224 and 1245 reduce the high-frequencycontent in the currents flowing through the circuit legs into the CKNand CKP terminals. The reduced high-frequency (i.e., band-limited)content of the currents flowing through the CKN and CKP terminals helpsreduce interference effects to other parts of the circuit, for example,the LNA circuitries, as described above. Capacitors 1233 and 1236 andresistors 1230 and 1251 help to further reduce the high-frequencycontent of the currents flowing through the CKN and CKP terminals. Thus,the circuit in FIG. 12 provides smooth steering of current between thetwo circuit legs and therefore reduces interference effects with othercircuitry.

[0144] When the enable signal goes to the low state, MOSFET device 1203turns on and causes MOSFET device 1209 to turn off. MOSFET devices 1227and 1248 also turn off, and the circuit becomes disabled. Note that theenable signal may be derived from the power-down PDNB signal.

[0145]FIG. 13A shows a schematic diagram of an exemplary embodiment1300A of a signal-receiver circuitry according to the invention. One mayuse the signal-receiver circuitry as the clock receiver circuitry 1130and the data receiver circuitry 1120 in FIG. 11A. In the latter case,the input signals to the signal-receiver circuitry constitute the IONand IOP signals 960 and 965 and the enable signal 1124, whereas theoutput signals constitute the signals at the outputs 1122A and 1122B,respectively, in FIG. 11A.

[0146] The signal receiver circuitry in FIG. 13A helps to convertdifferential input currents into CMOS logic signals. The signal-receivercircuitry in FIG. 13A constitutes two circuit legs. The first circuitleg includes MOSFET devices 1303, 1342, and 1345. The second legincludes MOSFET devices 1309, 1324, and 1327. Note that, preferably, thescaling of MOSFET devices 1303 and 1309 provides a current gain of 1:2between them. Likewise, the scaling of MOSFET devices 1330 and 1327preferably provides a current gain of 1:2 between them. The currentgains help to reduce phase noise in the signal-receiver circuitry.

[0147] MOSFET devices 1339, 1342, 1333, and 1324 provide enablecapability for the circuit. When the enable input is in the high state,MOSFET devices 1339, 1342, 1333, and 1324 are in the on state. MOSFETdevices 1345 and 1336 are current mirrors, as are MOSFET devices 1303and 1309. MOSFET devices 1330 and 1327 also constitute current mirrors.

[0148] The currents flowing through the CKN and CKP terminals mirror tothe MOSFET devices 1327 and 1309. The actual current flowing through thesecond circuit leg depends on the currents that MOSFET device 1327 andMOSFET device 1309 try to conduct; the lower of the two currentsdetermines the actual current that flows through the second circuit leg.

[0149] The difference between the currents that MOSFET device 1327 andMOSFET device 1309 try to conduct flows through the parasiticcapacitance at node 1360. The current flow charges or discharges thecapacitance at node 1360, thus making smaller the drain-source voltage(V_(ds)) of whichever of MOSFET devices 1327 and 1309 that seeks tocarry the higher current. Ultimately, the lower of the currents thatMOSFET devices 1327 and 1309 seek to conduct determines the currentthrough the second leg of the circuit.

[0150] A pair of inverters 1312 and 1315 provide true and complementoutput signals 1351 and 1348, respectively. The signal receivercircuitry therefore converts differential input currents into CMOS logicoutput signals.

[0151] In exemplary embodiments of the invention, the signal receivercircuitry provides fully differential output signals. FIG. 13B shows anembodiment 1300B of such a signal receiver circuitry. One may useembodiment 1300B in a similar manner and application as embodiment1300A, using the same input signals, as desired. Unlike embodiment1300A, however, embodiment 1300B includes fully differential circuitryto generate fully differential output signals.

[0152] Embodiment 1300B includes the same devices as does embodiment1300A, and the common devices operate in a similar manner. Furthermore,embodiment 1300B includes additional devices and components. Embodiment1300B constitutes two circuit legs and replica of those circuit legs.The first circuit leg includes MOSFET devices 1303, 1342, and 1345. Thereplica of the first circuit leg includes devices 1355, 1379, and 1381.The second circuit leg includes MOSFET devices 1309, 1324, and 1327. Thereplica of the second circuit leg include devices 1357, 1363, and 1365.The scaling of MOSFET devices 1303 and 1309 provides a current gain of1:2 between them, as does the scaling of MOSFET devices 1330 and 1327.Likewise, scaling of MOSFET devices 1355 and 1357 provides a currentgain of 1:2 between them, as does the scaling of MOSFET devices 1336 and1365. The current gains help to reduce phase noise in thesignal-receiver circuitry.

[0153] Embodiment 1300B generally operates similarly to embodiment1300A. Devices 1381, 1379, 1355, 1353, 1357, 1363, 1365, 1367, 1369,1359, and 1361 perform the same functions as do devices 1345, 1342,1303, 1306, 1309, 1324, 1327, 1321, 1318, 1312, and 1315, respectively.The enable function also operates similarly to embodiment 1300A.Resistors 1371 and 1375 and capacitors 1373 and 1377 filter the inputclock (e.g., 13 MHz clock). Inverters 1312, 1315, 1361, and 1359 providefully differential true and complement output signals.

[0154]FIG. 14 shows an embodiment 1400 of an alternative signal-drivercircuitry according to the invention. The signal-driver circuitry inFIG. 14 includes two circuit legs. The first circuit leg includes MOSFETdevice 1406 and resistor 1415A. The second circuit leg includes MOSFETdevice 1409 and resistor 1415B. A current source 1403 supplies currentto the two circuit legs.

[0155] The input clock signal controls MOSFET devices 1406 and 1409.MOSFET devices 1406 and 1409 drive the CKP and CKN output terminals,respectively. Depending on the state of the clock signal, one leg of thesignal-driver circuitry conducts current. Put another way, thesignal-driver circuitry steers current from one leg to the other inresponse to the clock signal. As a result, the signal-driver circuitryprovides a differential clock signal that includes signals CKN and CKP.Capacitor 1412 filters the output signals CKN and CKP. Put another way,capacitor 1412 provides band-limiting of the output signals CKN and CKP.Note that the current source 1403 supplies limited-amplitude signals byproviding current through resistors 1415A and 1415B.

[0156] Note that the signal-driver circuitries (clock driver and datadriver circuitries) according to the invention preferably providecurrent signals CKN and CKP. Similarly, signal-receiver circuitries(clock receiver and data receiver circuitries) according to theinvention preferably receive current signals. As an alternative, one mayuse signal-driver circuitries that provide as their outputs voltagesignals, as desired. One may also implement signal-receiver circuitriesthat receive voltage signals, rather than current signals. As notedabove, depending on the application, one may limit the frequencycontents of those voltage signals, for example, by filtering, asdesired.

[0157] Generally, several techniques exist for limiting noise, forexample, digital switching-noise, in the interface between the receiveranalog circuitry and the receiver digital circuitry according to theinvention. Those techniques include using differential signals, usingband-limited signals, and using amplitude-limited signals. RF apparatusaccording to the invention may use any or all of those techniques, asdesired. Furthermore, one may apply any or all of those techniques tointerface circuitry that employs voltage or current signals, as personsof ordinary skill in the art who have the benefit of the description ofthe invention understand.

[0158] Note also that the RF transceiver embodiments according to theinvention lend themselves to various choices of circuit implementation,as a person skilled in the art who have the benefit of the descriptionof the invention understand. For example, as noted above, each of thecircuit partitions, or circuit blocks, of RF transceivers partitionedaccording to the invention, resides preferably within an integratedcircuit device. Persons skilled in the art, however, will appreciatethat the circuit partitions, or circuit blocks, may alternatively residewithin other substrates, carriers, or packaging arrangements. By way ofillustration, other partitioning arrangements may use modules, thin-filmmodules, thick-film modules, isolated partitions on a single substrate,circuit-board partitions, and the like, as desired, consistent with theembodiments of the invention described here.

[0159] One aspect of the invention contemplates partitioning RFtransceivers designed to operate within several communication channels(e.g., GSM, PCS, and DCS). Persons skilled in the art, however, willrecognize that one may partition according to the invention RFtransceivers designed to operate within one or more other channels,frequencies, or frequency bands, as desired.

[0160] Moreover, the partitioning of RF transceivers according to theinvention preferably applies to RF apparatus (e.g., receivers ortransceivers) with a low-IF, digital-IF architecture. Note, however,that one may apply the partitioning and interfacing concepts accordingto the invention to other RF receiver or transceiver architectures andconfigurations, as persons of ordinary skill in the art who have thebenefit of the description of the invention understand. By way ofillustration, one may use the partitioning and interface conceptsaccording to the invention in RF apparatus that includes:

[0161] low-IF receiver circuitry;

[0162] low-IF receiver circuitry and offset-PLL transmitter circuitry;

[0163] low-IF receiver circuitry and direct up-conversion transmittercircuitry;

[0164] direct-conversion receiver circuitry;

[0165] direct-conversion receiver circuitry and offset-PLL transmittercircuitry; or

[0166] direct-conversion receiver circuitry and direct up-conversiontransmitter circuitry.

[0167] As an example of the flexibility of the partitioning conceptsaccording to the invention, one may include the LO circuitry in onepartition, the receiver digital circuitry in a second partition, and thetransmitter up-converter circuitry and the receiver analog circuitry ina third partition. As another illustrative alternative, one may includethe LO circuitry and the transmitter up-converter circuitry within onecircuit partition, depending on the noise and interferencecharacteristics and specifications for a particular implementation.

[0168] Note that, in a typical direct-conversion RF receiver ortransceiver implementation, the receiver digital circuitry would notinclude the digital down-converter circuitry (the receiver analogcircuitry, however, would be similar to the embodiments describedabove). Furthermore, in a typical direct up-conversion transmittercircuitry, one would remove the offset PLL circuitry and the transmitVCO circuitry from the transmitter circuitry. The LO circuitry wouldsupply the RF LO signal to the up-conversion circuitry of thetransmitter circuitry, rather than the offset-PLL circuitry. Also, in adirect up-conversion implementation, the LO circuitry typically does notprovide an IF LO signal.

[0169] Furthermore, as noted above, one may use the partitioning andinterface concepts according to the invention not only in RFtransceivers, but also in RF receivers for high-performanceapplications. In such RF receivers, one may partition the receiver asshown in FIGS. 2A-2D and 4-8, and as described above. In other words,the RF receiver may have a first circuit partition that includes thereceiver analog circuitry, and a second circuit partition that includesthe receiver digital circuitry.

[0170] The RF receiver may also use the digital interface between thereceiver analog circuitry and the receiver digital circuitry, asdesired. By virtue of using the receiver analog circuitry and thereceiver digital circuitry described above, the RF receiver features alow-IF, digital-IF architecture. In addition, as noted above withrespect to RF transceivers according to the invention, depending onperformance specifications and design goals, one may include all or partof the local oscillator circuitry within the circuit partition thatincludes the receiver analog circuitry, as desired. Partitioning RFreceivers according to the invention tends to reduce the interferenceeffects between the circuit partitions.

[0171] As noted above, although RF apparatus according to the inventionuse a serial interface between the receiver analog circuitry and thereceiver digital circuitry, one may use other types of interface, forexample, parallel interfaces, that incorporate different numbers ofsignal lines, different types and sizes of signals, or both, as desired.Moreover, the clock driver circuitries and the data driver circuitriesmay generally constitute signal-driver circuitries that one may use in avariety of digital interfaces between the receiver analog circuitry andthe receiver digital circuitry according to the invention.

[0172] Likewise, the clock receiver circuitries and data receivercircuitries may generally constitute signal-receiver circuitries thatone may use in a variety of digital interfaces between the receiveranalog circuitry and the receiver digital circuitry according to theinvention. In other words, one may use signal-driver circuitries andsignal-receiver circuitries to implement a wide variety of digitalinterfaces, as persons of ordinary skill who have the benefit of thedescription of the invention understand.

[0173] Another aspect of the invention relates to improvedquadrature-signal generation. One may use apparatus and methods forimproved quadrature-signal generation in various RF receivers andtransceivers, such as low-IF and direct-conversion receivers andtransceivers, as desired.

[0174]FIG. 15 shows a block diagram of a portion of receive-pathcircuitry in a low-IF or direct conversion RF receiver. The RF inputsignal, as amplified by optional amplifier 1500 (e.g., LNA circuitry 824in FIG. 8), provides one input signal of mixer 1503 and one input signalof mixer 1506. An LO signal drives an input of phase-shifter 1509.Phase-shifter 1509 derives output signal 1521 and output signal 1524from the LO signal. Output signal 1521 and output signal 1524 have a90°, or π/2 radians, phase difference. Output signal 1521 constitutes asecond input of mixer 1503, whereas output signal 1524 constitutes asecond input of mixer 1506.

[0175] Mixer 1503 and mixer 1506 generate mixer output signal 1512 andmixer output signal 1515, respectively. Because of mixing using signalsthat have a 90° phase shift, mixer output signal 1512 constitutes anin-phase signal, and mixer output signal 1515 constitutes a quadraturesignal. Mixer output signal 1512 and mixer output signal 1515 drivecircuitry 1518. In a low-IF receiver or transceiver, circuitry 1518constitutes low-IF receive circuitry and baseband circuitry. In adirect-conversion receiver or transceiver, circuitry 1518 constitutesbaseband circuitry.

[0176] For improved performance of the RF receiver or transceiver, mixeroutput signal 1512 and mixer output signal 1515 should have a quadraturerelationship to each other. Thus, phase-shifter 1509 should generateoutput signals 1521 and 1524 such that their phase difference is asclose to 90°, or π/2 radians, as possible.

[0177] Typically, phase-shifter 1509 uses divide-by-two circuitry or apoly-phase filter to generate output signals 1521 and 1524 (i.e.,generate quadrature signals). FIG. 16 shows a quadrature-generationcircuit that uses poly-phase filter 1605. The signals in FIG. 16constitute differential signals, although one may use single-endedsignals, as persons of ordinary skill in the art with the benefit of thedescription of the invention understand.

[0178] Buffer 1603 buffers the LO signal, and provides the resultingsignal to poly-phase filter 1605. Buffer 1603 generally constitutes anon-linear block. As a consequence, its output includes harmoniccontents. Poly-phase filter 1605 generates the in-phase (1) andquadrature (Q) signals at its outputs, which its supplies to limiter1610 and limiter 1615, respectively.

[0179] Limiter 1610 and limiter 1615 generate output signal 1521 andoutput signal 1524 (see FIG. 15), which drive mixer 1503 and mixer 1506,respectively. Limiter 1610 and limiter 1615 may constitute additionalgain stages that boost the power of the I and Q signals from poly-phasefilter 1605 before the mixing operation in mixer 1503 and mixer 1506.(Note that, alternatively, limiter 1610 and limiter 1615 may representthe limiting action present in mixer 1503 and mixer 1506, respectively.)

[0180]FIG. 17 shows a plot versus frequency of the magnitude of transferfunction 1703 of poly-phase filter 1605. Note that poly-phase filter1605 provides a notch at the LO frequency, +f_(LO). Thus, by notchingthe positive frequency at +f_(LO), poly-phase filter 1605 transmits(albeit with some attenuation) the component at −f_(LO). One maymathematically represent the component at −f_(LO) as having a cosinecomponent and a sine component or, in other words, as two signals havinga quadrature relationship (shown as signals I and Q at the output ofpoly-phase 1605 in FIG. 16).

[0181] More specifically, one may represent the LO signal as:${{{LO}(t)} = {{A\quad \cos \quad \omega_{LO}t} = {\frac{1}{2}{A\left( {\,^{j\quad \omega_{LO}t}{+ ^{{- j}\quad \omega_{LO}t}}} \right)}}}},$

[0182] where A and ω_(LO) represent the amplitude and radian frequencyof the LO signal, respectively. Poly-phase filter 1605 filters the firstcomplex exponential term (corresponding to the component at +f_(LO)),leaving the second complex exponential term. In other words, one mayrepresent the output of poly-phase filter 1605, Output(t), as:${{Output}\quad (t)} = {{\frac{1}{2}A\quad ^{{- j}\quad \omega_{LO}t}} = {{\frac{1}{2}A\quad \cos \quad \omega_{LO}t} - {\frac{1}{2}A\quad \sin \quad \omega_{LO}{t.}}}}$

[0183] As the above equation indicates, the output of poly-phase filter1605 has an in-phase component and a quadrature component that have a90° phase shift between them.

[0184]FIG. 18 illustrates a spectrum of the output of poly-phase filter1605 shown in FIG. 16. Note that the spectrum in FIG. 18 includesharmonics of the LO signal (e.g., harmonics at −3f_(LO) and +3f_(LO)).Circuit non-linearity, for example, non-linearity in buffer 1603 (seeFIG. 16) give rise to the harmonics shown in FIG. 18. Referring to FIG.16, note that the circuitry after poly-phase filter 1605 also containsnon-linear elements. For example, limiter 1610 and limiter 1615constitute non-linear circuits.

[0185] Because of the non-linearity present in the circuit, the thirdharmonic may fold over to the positive LO frequency, +f_(LO). Thespectral component at +f_(LO) consequently degrades the quadraturerelationship between the I and Q signals at the output of poly-phasefilter 1605 (see FIG. 16). FIG. 19 shows a graphical representation ofthe folding over of the frequency component present at the −3f_(LO)(i.e., third harmonic) to the positive fundamental frequency, +f_(LO).

[0186] The degradation in the quadrature relationship between the I andQ signals at the output of poly-phase filter 1605 has detrimentaleffects on the performance of the RF receiver or transceiver. Theresulting third harmonic limits or degrades the image rejection ratio ofthe RF receiver or transceiver. As a result, achieving image rejectionratios greater than 30 dB may prove difficult as a result of thenon-linear mechanisms described above.

[0187]FIG. 20 shows a circuit arrangement 2000 for improved quadraturesignal generation according to an illustrative embodiment of theinvention. One may use circuit arrangement 2000 in either low-IF ordirection-conversion receivers and/or transceivers, as desired. Buffer1603 buffers the LO signal, and provides the resulting signal topoly-phase filter 1605. Poly-phase filter 1605 generates in-phase (1)and quadrature (Q) signals at its output, and provides those signals toharmonic filter 2005. Harmonic filter 2005 filters prescribed harmonicsof the LO frequency. In the embodiment shown in FIG. 20, harmonic filter2005 filters the third harmonic of the LO signal, i.e., the componenthaving a frequency of 3f_(LO).

[0188] Harmonic filter 2005 generates output signal 2010 and outputsignal 2015, which its supplies to limiter 1610 and limiter 1615,respectively. Limiter 1610 and limiter 1615 generate output signal 1521and output signal 1524 (see FIG. 15), which drive mixer 1503 and mixer1506, respectively. As noted above, limiter 1610 and limiter 1615 mayconstitute additional gain stages that boost the power of the I and Qsignals from poly-phase filter 1605 before the mixing operation in mixer1503 and mixer 1506. (Also as noted above, alternatively, limiter 1610and limiter 1615 may represent the limiting action present in mixer 1503and mixer 1506, respectively.)

[0189] By filtering or eliminating the third harmonic of the LO signal,harmonic filter 2005 tends to reduce or eliminate the third harmonicthat would otherwise fold over to the positive LO frequency. As aconsequence, output signal 1521 and output signal 1524 have an improvedquadrature relationship to each other. Thus, the RF receiver ortransceiver including circuit arrangement 2000 tends to have improvedperformance, for example, a greater image rejection ratio.

[0190] As persons of ordinary skill in the art with the benefit of thedescription of the invention understand, one may reverse the order ofpoly-phase filter 1605 and harmonic filter 2005. In other words, one maydrive harmonic filter 2005 with the output of buffer 1603, and drivepoly-phase filter 1605 with the outputs of harmonic filter 2005.

[0191] Harmonic filter 2005 may constitute a passive filter or an activefilter, as desired. Furthermore, harmonic filter 2005 may constitute areal filter or a complex filter, as desired. FIG. 21 shows anillustrative embodiment 2100 of a harmonic filter according to theinvention. The filter in embodiment 2100 constitutes a passive RC filterfor each of the in-phase and quadrature signal paths. Note that,although embodiment 2100 provides a single-ended filter, one may providea differential filter by making modifications that fall within theknowledge of persons skilled in the art with the benefit of thedescription of the invention.

[0192] In order to filter the third harmonic of the LO signal, one maychoose the values of the resistor R and capacitor C in embodiment 2100such that:$\frac{1}{2\pi \quad {RC}}{\operatorname{<<}\quad 3}{f_{LO}.}$

[0193] Note that to filter the third harmonic (relative to thefundamental frequency), one should select the corner frequency (or −3 dBfrequency) for each of the RC filters in FIG. 21 at a value less thanf_(LO) to achieve at least 10 dB of attenuation of the third-harmoniccomponent. Doing so, however, attenuates the fundamental LO frequencyitself.

[0194] One may use a variety of filter structures to implement harmonicfilter 2005 (see FIG. 20). FIG. 22 shows an illustrative embodiment 2200of another harmonic filter according to the invention. The filter inembodiment 2200 constitutes a complex passive filter. One may design thefilter in embodiment 2200 so that it filters the positive component ofthe third harmonic or the negative component of the third harmonic, asdesired, and as persons skilled in the art with the benefit of thedescription of the invention understand.

[0195] In order to filter the third harmonic of the LO signal, one maychoose the values of the resistor R and capacitor C in embodiment 2200such that: $\frac{1}{2\pi \quad {RC}} = \quad {3{f_{LO}.}}$

[0196]FIG. 23 shows a plot versus frequency of the magnitude of transferfunction 2300 of poly-phase filter 1605 and harmonic filter 2005 (i.e.,the transfer function between the output of harmonic filter 2005 and theinput of poly-phase filter 1605). As noted above, poly-phase filter 1605provides a notch at the LO frequency, +f_(LO). Harmonic filter 2005, asdesigned above, filters the negative third-harmonic component (i.e., thecomponent at −3f_(LO)). Note that, although the filter in embodiment2200 filters the third-harmonic component relatively well, itnevertheless filters the fundamental frequency (i.e., at −f_(LO)) tosome degree. Note further that, although embodiment 2200 constitutes adifferential filter, one may provide a single-ended filter by makingmodifications that fall within the knowledge of persons skilled in theart with the benefit of the description of the invention.

[0197]FIG. 24 shows an illustrative embodiment 2400 of another harmonicfilter according to the invention. The filter in embodiment 2400constitutes an active filter. More specifically, it constitutes a“g_(m)/C” filter, or a filter in which a transconductance stage oramplifier drives a capacitive load. The filter in embodiment 2400provides a compromise between gain at the fundamental frequency, andrejection of the harmonic frequencies, e.g., the third harmonic.

[0198] Note that both the filter may provide gain at both thefundamental frequency and the harmonic frequencies, but the gain at thefundamental frequency is larger than at the harmonic frequencies.Furthermore, note that, given the filter in embodiment 2400 ideallyconstitutes an integrator, it attenuates (with respect to thefundamental frequency) the third harmonic by 10 dB regardless of theunity-gain value of the g_(m)/C circuit arrangement. If the unity-gainvalue of the g_(m)/C circuit arrangement exceeds 2πf_(LO), then thefilter amplifies, rather than attenuates, at the fundamental LOfrequency. Note that, although embodiment 2100 provides a single-endedfilter, one may provide a differential filter by making modificationsthat fall within the knowledge of persons skilled in the art with thebenefit of the description of the invention.

[0199]FIG. 25 shows an illustrative embodiment 2500 of an implementationof an active harmonic filter (and corresponding limiter) according tothe invention. Embodiment 2500 as shown in FIG. 25 constitutes adifferential active harmonic filter and accompanying limiter for thein-phase (I) signal path.

[0200] Embodiment 2500 includes two circuit arrangements that may bemirror images of one another, as desired. The first circuit arrangementincludes a cascade coupling of capacitor 2505A (labeled as C₁),transconductance or gm stage 2510A, and limiter stage 2515A. The firstcircuit arrangement accepts in-phase input signal I_(p), and providesin-phase output signal I_(p)′.

[0201] Referring to the first circuit arrangement in embodiment 2500,transconductance or g_(m) stage 2510A accepts the input signal I_(p)through capacitor 2505A. Transconductance or g_(m) stage 2510A uses twotransistors, one p-type and one n-type, coupled as an inverter.Transconductance or gm stage 2510A also includes resistor 2520A (labeledas R₁), which couples the output of transconductance or g_(m) stage2510A to its output. The output of transconductance or g_(m) stage 2510Adrives limiter stage 2515A.

[0202] Limiter stage 2515A uses two transistors, one p-type and onen-type, essentially coupled as an inverter. The input capacitance oflimiter stage 2515A (e.g., the gate-source capacitance of the twotransistors in limiter state 2515A) serves as the capacitance C in theg_(m)/C filter. In embodiment 2500, transconductance or gm stage 2510Aand limiter stage 2515A use MOSFETs (i.e., they use CMOS circuitry).

[0203] Referring to FIG. 25, the second circuit arrangement is similarto the first circuit arrangement. The second circuit arrangement inembodiment 2500 includes a cascade coupling of capacitor 2505B (labeledas C₁), transconductance or gm stage 2510B, and limiter stage 2515B. Thefirst circuit arrangement accepts in-phase input signal I_(n), andprovides in-phase output signal I_(n)′.

[0204] Transconductance or g_(m) stage 2510B accepts the input signalI_(n) through capacitor 2505B. Transconductance or g_(m) stage 2510Buses two transistors, one p-type and one n-type, coupled as an inverter.Transconductance or g_(m) stage 2510B also includes resistor 2520B(labeled as R₁), which couples the output of transconductance or g_(m)stage 2510B to its output. The output of transconductance or gm stage2510A drives limiter stage 2515B. Limiter stage 2515B uses twotransistors, one p-type and one n-type, essentially coupled as aninverter. The input capacitance of limiter stage 2515B (e.g., thegate-source capacitance of the two transistors in limiter state 2515B)serves as the capacitance C in the g_(m)/C filter. In embodiment 2500,transconductance or g_(m) stage 2510B and limiter stage 2515B useMOSFETs (i.e., they use CMOS circuitry).

[0205] As persons of ordinary skill in the art who have the benefit ofthe description of the invention understand, embodiment 2500 providesmerely one implementation of an active filter. Generally, FIGS. 21, 22,24, and 25 show merely illustrative embodiments of filters according tothe invention. One may use a variety of other filter structures andcircuit arrangements to implement harmonic filter 2005 (and othercircuit elements, such as the limiters), as desired.

[0206] For example, one may use different types of transistor (e.g.,bipolar junction transistors, or BJTs), as desired. As another example,one may choose not to use the input capacitance of the limiters as thecapacitance C in g_(m)/C filters, as desired, depending on such factorsas whether the LO signal has a large enough magnitude without usinglimiter stages 2515A and 2515B (e.g., one may use a capacitor C, ratherthan the input capacitance of a limiter). The choice of the filterstructure and circuit arrangement depends on factors such as design andperformance specifications for a given implementation, as artisans withthe benefit of the description of the invention understand.

[0207] Note that embodiment 2500 shows a filter for the in-phase (I)signal path. One may replicate the circuit arrangement in embodiment2500 to provide filtering for the quadrature (Q) signal path. Notefurther that, although embodiment 2500 provides a differential filter,one may provide a single-ended filter by making modifications that fallwithin the knowledge of persons skilled in the art with the benefit ofthe description of the invention.

[0208] Referring to the figures, the various blocks shown depict mainlythe conceptual functions and signal flow. The actual circuitimplementation may or may not contain separately identifiable hardwarefor the various functional blocks. For example, one may combine thefunctionality of various blocks into one circuit block, as desired.Furthermore, one may realize the functionality of a single block inseveral circuit blocks, as desired. The choice of circuit implementationdepends on various factors, such as particular design and performancespecifications for a given implementation, as persons of ordinary skillin the art who have the benefit of the disclosure of the inventionunderstand.

[0209] Further modifications and alternative embodiments of thisinvention will be apparent to persons skilled in the art in view of thisdescription of the invention. Accordingly, this description teachesthose skilled in the art the manner of carrying out the invention andare to be construed as illustrative only.

[0210] The forms of the invention shown and described should be taken asthe presently preferred embodiments. Persons skilled in the art may makevarious changes in the shape, size and arrangement of parts withoutdeparting from the scope of the invention described in this document.For example, persons skilled in the art may substitute equivalentelements for the elements illustrated and described here. Moreover,persons skilled in the art who have the benefit of this description ofthe invention may use certain features of the invention independently ofthe use of other features, without departing from the scope of theinvention.

I claim:
 1. A radio-frequency (RF) apparatus, comprising: receive-pathcircuitry, comprising: a poly-phase filter, the poly-phase filterconfigured to accept an input signal and provide a first in-phase signaland a first quadrature signal; and a harmonic filter coupled to thepoly-phase filter, the harmonic filter configured to accept the firstin-phase signal and the first quadrature signal.
 2. The radio-frequency(RF) apparatus according to claim 1, wherein the harmonic filter isfurther configured to provide a second in-phase signal and a secondquadrature signal.
 3. The radio-frequency (RF) apparatus according toclaim 2, wherein the harmonic filter is further configured to filter athird harmonic frequency of the input signal of the poly-phase filter.4. The radio-frequency (RF) apparatus according to claim 3, wherein theharmonic filter comprises a passive filter.
 5. The radio-frequency (RF)apparatus according to claim 3, wherein the harmonic filter comprises apassive complex filter.
 6. The radio-frequency (RF) apparatus accordingto claim 3, wherein the harmonic filter comprises an active filter. 7.The radio-frequency (RF) apparatus according to claim 6, wherein theharmonic filter further comprises a transconductance circuitry coupledto a capacitor.
 8. The radio-frequency (RF) apparatus according to claim7, wherein the harmonic filter comprises complementary metal oxidesemiconductor (CMOS) circuitry.
 9. The radio-frequency (RF) apparatusaccording to claim 7, wherein the capacitor comprises an inputcapacitance of a limiter coupled to the harmonic filter.
 10. Theradio-frequency (RF) apparatus according to claim 3, further comprisinga buffer coupled to the poly-phase filter, the buffer configured toaccept a local oscillator signal, the buffer further configured toprovide the input signal of the poly-phase filter.
 11. Theradio-frequency (RF) apparatus according to claim 10, furthercomprising: a first mixer coupled to the harmonic filter, the firstmixer configured to mix a radio-frequency (RF) signal with the secondin-phase signal; and a second mixer coupled to the harmonic filter, thesecond mixer configured to mix the ratio-frequency (RF) signal with thesecond quadrature signal.
 12. The radio-frequency (RF) apparatusaccording to claim 10, further comprising: a first limiter coupled tothe harmonic filter, the first limiter configured to accept the secondin-phase signal, the first limiter further configured to generate athird in-phase signal; and a second limiter coupled to the harmonicfilter, the second limiter configured to accept the second quadraturesignal, the second limiter further configured to generate a thirdquadrature signal.
 13. The radio-frequency (RF) apparatus according toclaim 12, further comprising: a first mixer coupled to the firstlimiter, the first mixer configured to mix a radio-frequency (RF) signalwith the third in-phase signal; and a second mixer coupled to the secondlimiter, the second mixer configured to mix the ratio-frequency (RF)signal with the third quadrature signal.
 14. The radio-frequency (RF)apparatus according to claim 3, wherein the receive-path circuitrycomprises low-intermediate-frequency (low-IF) circuitry.
 15. Theradio-frequency (RF) apparatus according to claim 3, wherein thereceive-path circuitry comprises direct-conversion circuitry.
 16. Aradio-frequency (RF) apparatus, comprising: receive-path circuitry,comprising: a harmonic filter, the harmonic filter configured to acceptan input signal and to provide an output signal; and a poly-phase filtercoupled to the harmonic filter, the poly-phase filter configured toaccept the output signal of the harmonic filter.
 17. The radio-frequency(RF) apparatus according to claim 16, wherein the poly-phase filter isfurther configured to provide a second in-phase signal and a secondquadrature signal.
 18. The radio-frequency (RF) apparatus according toclaim 17, wherein the harmonic filter is further configured to filter athird harmonic frequency of the input signal.
 19. The radio-frequency(RF) apparatus according to claim 18, wherein the harmonic filtercomprises a passive filter.
 20. The radio-frequency (RF) apparatusaccording to claim 18, wherein the harmonic filter comprises a passivecomplex filter.
 21. The radio-frequency (RF) apparatus according toclaim 18, wherein the harmonic filter comprises an active filter. 22.The radio-frequency (RF) apparatus according to claim 21, wherein theharmonic filter further comprises a transconductance circuitry coupledto a capacitor.
 23. The radio-frequency (RF) apparatus according toclaim 22, wherein the harmonic filter comprises complementary metaloxide semiconductor (CMOS) circuitry.
 24. A method of generatingquadrature signals in a radio-frequency (RF) apparatus, the methodcomprising: filtering an input signal in a poly-phase filter; generatinga first in-phase signal and a first quadrature signal; and filtering thefirst in-phase signal and the first quadrature signal in a harmonicfilter.
 25. The method according to claim 24, further comprisinggenerating a second in-phase signal and a second quadrature signal withthe harmonic filter.
 26. The method according to claim 25, whereinfiltering the first in-phase signal and the first quadrature signal inthe harmonic filter further comprises filtering a third harmonicfrequency of the output signal of the poly-phase filter.
 27. The methodaccording to claim 26, wherein the harmonic filter in filtering thefirst in-phase signal and the first quadrature signal comprises apassive filter.
 28. The method according to claim 26, wherein theharmonic filter in filtering the first in-phase signal and the firstquadrature signal comprises an active filter.
 29. The method accordingto claim 26, wherein the harmonic filter comprises an active filter.